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Revert "gpu: nvgpu: cache gpu clk rate"

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This reverts commit e9a6d179a4 ("gpu: nvgpu: cache gpu clk rate")

 - Real clock rate doesn't always equal clock rate requested by caller
 - call of clk_set_rate() and update of cached_rate are not atomic
 - Real root cause for Bug 2051688 is in bpmp and gboost design


Bug 2538692

Change-Id: I9248e0c69e2271ed2d0070587db59afa6f8160f2
Signed-off-by: Peng Liu <pengliu@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2109708
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Alex Waterman <alexw@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
This commit is contained in:
Peng Liu
2019-03-13 10:30:54 -07:00
committed by mobile promotions
parent 1374fba039
commit cc70f89bb4
5 changed files with 5 additions and 24 deletions
Download Patch File Download Diff File Expand all files Collapse all files

3
drivers/gpu/nvgpu/hal/clk/clk_gk20a.h
View File

@@ -96,9 +96,6 @@ struct clk_gk20a {
#if defined(CONFIG_COMMON_CLK) #if defined(CONFIG_COMMON_CLK)
struct clk *tegra_clk; struct clk *tegra_clk;
struct clk_hw hw; struct clk_hw hw;
/* scaling rate */
unsigned long cached_rate;
#endif #endif
struct pll gpc_pll; struct pll gpc_pll;
struct pll gpc_pll_last; struct pll gpc_pll_last;

19
drivers/gpu/nvgpu/os/linux/clk.c
View File

@@ -1,7 +1,7 @@
/* /*
* Linux clock support * Linux clock support
* *
* Copyright (c) 2017-2018, NVIDIA CORPORATION. All rights reserved. * Copyright (c) 2017-2019, NVIDIA CORPORATION. All rights reserved.
* *
* This program is free software; you can redistribute it and/or modify it * This program is free software; you can redistribute it and/or modify it
* under the terms and conditions of the GNU General Public License, * under the terms and conditions of the GNU General Public License,
@@ -38,13 +38,9 @@ static unsigned long nvgpu_linux_clk_get_rate(struct gk20a *g, u32 api_domain)
switch (api_domain) { switch (api_domain) {
case CTRL_CLK_DOMAIN_GPCCLK: case CTRL_CLK_DOMAIN_GPCCLK:
if (g->clk.tegra_clk) if (g->clk.tegra_clk)
ret = g->clk.cached_rate ? ret = clk_get_rate(g->clk.tegra_clk);
g->clk.cached_rate :
clk_get_rate(g->clk.tegra_clk);
else else
ret = platform->cached_rate ? ret = clk_get_rate(platform->clk[0]);
platform->cached_rate :
clk_get_rate(platform->clk[0]);
break; break;
case CTRL_CLK_DOMAIN_PWRCLK: case CTRL_CLK_DOMAIN_PWRCLK:
ret = clk_get_rate(platform->clk[1]); ret = clk_get_rate(platform->clk[1]);
@@ -66,15 +62,10 @@ static int nvgpu_linux_clk_set_rate(struct gk20a *g,
switch (api_domain) { switch (api_domain) {
case CTRL_CLK_DOMAIN_GPCCLK: case CTRL_CLK_DOMAIN_GPCCLK:
if (g->clk.tegra_clk) { if (g->clk.tegra_clk)
ret = clk_set_rate(g->clk.tegra_clk, rate); ret = clk_set_rate(g->clk.tegra_clk, rate);
if (!ret) else
g->clk.cached_rate = rate;
} else {
ret = clk_set_rate(platform->clk[0], rate); ret = clk_set_rate(platform->clk[0], rate);
if (!ret)
platform->cached_rate = rate;
}
break; break;
case CTRL_CLK_DOMAIN_PWRCLK: case CTRL_CLK_DOMAIN_PWRCLK:
ret = clk_set_rate(platform->clk[1], rate); ret = clk_set_rate(platform->clk[1], rate);

3
drivers/gpu/nvgpu/os/linux/platform_gk20a.h
View File

@@ -300,9 +300,6 @@ struct gk20a_platform {
/* stream id to use */ /* stream id to use */
u32 ltc_streamid; u32 ltc_streamid;
/* scaling rate */
unsigned long cached_rate;
/* synchronized access to platform->clk_get_freqs */ /* synchronized access to platform->clk_get_freqs */
struct nvgpu_mutex clk_get_freq_lock; struct nvgpu_mutex clk_get_freq_lock;
}; };

2
drivers/gpu/nvgpu/os/linux/platform_gk20a_tegra.c
View File

@@ -496,8 +496,6 @@ static int gk20a_tegra_get_clocks(struct device *dev)
rate = clk_round_rate(c, rate); rate = clk_round_rate(c, rate);
clk_set_rate(c, rate); clk_set_rate(c, rate);
platform->clk[i] = c; platform->clk[i] = c;
if (i == 0)
platform->cached_rate = rate;
} }
platform->num_clks = i; platform->num_clks = i;

2
drivers/gpu/nvgpu/os/linux/platform_gp10b_tegra.c
View File

@@ -95,8 +95,6 @@ int gp10b_tegra_get_clocks(struct device *dev)
} else { } else {
clk_set_rate(c, rate); clk_set_rate(c, rate);
platform->clk[i] = c; platform->clk[i] = c;
if (i == 0)
platform->cached_rate = rate;
} }
} }
platform->num_clks = i; platform->num_clks = i;