gpu: nvgpu: pass pid/tid from os specific code to common code

linux driver runs in user's process but qnx driver has dedicate driver
process, so they have different way to get user pid. nvgpu common code
expect calls from os specific code pass pid/tid.

ce/cde open channel for internal use, we use driver pid.

Jira VQRM-3534

Change-Id: I892372ac5f1dc4d25f9928d16992bcc659d12a56
Signed-off-by: Richard Zhao <rizhao@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1694145
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>

drivers/gpu/nvgpu/common/linux/cde.c

@@ -31,6 +31,7 @@
 #include <nvgpu/log.h>
 #include <nvgpu/bug.h>
 #include <nvgpu/firmware.h>
+#include <nvgpu/os_sched.h>
 
 #include <nvgpu/linux/vm.h>
 
@@ -1287,7 +1288,7 @@ static int gk20a_cde_load(struct gk20a_cde_ctx *cde_ctx)
 		return -ENOSYS;
 	}
 
-	tsg = gk20a_tsg_open(g);
+	tsg = gk20a_tsg_open(g, nvgpu_current_pid(g));
 	if (!tsg) {
 		nvgpu_err(g, "cde: could not create TSG");
 		err = -ENOMEM;

drivers/gpu/nvgpu/common/linux/channel.c

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2017, NVIDIA Corporation.  All rights reserved.
+ * Copyright (c) 2017-2018, NVIDIA Corporation.  All rights reserved.
  *
  * This program is free software; you can redistribute it and/or modify it
  * under the terms and conditions of the GNU General Public License,
@@ -18,6 +18,7 @@
 #include <nvgpu/debug.h>
 #include <nvgpu/ltc.h>
 #include <nvgpu/error_notifier.h>
+#include <nvgpu/os_sched.h>
 
 /*
  * This is required for nvgpu_vm_find_buf() which is used in the tracing
@@ -251,7 +252,8 @@ struct channel_gk20a *gk20a_open_new_channel_with_cb(struct gk20a *g,
 	struct channel_gk20a *ch;
 	struct nvgpu_channel_linux *priv;
 
-	ch = gk20a_open_new_channel(g, runlist_id, is_privileged_channel);
+	ch = gk20a_open_new_channel(g, runlist_id, is_privileged_channel,
+				nvgpu_current_pid(g), nvgpu_current_tid(g));
 
 	if (ch) {
 		priv = ch->os_priv;

drivers/gpu/nvgpu/common/linux/ioctl_channel.c

@@ -1,7 +1,7 @@
 /*
  * GK20A Graphics channel
  *
- * Copyright (c) 2011-2017, NVIDIA CORPORATION.  All rights reserved.
+ * Copyright (c) 2011-2018, NVIDIA CORPORATION.  All rights reserved.
  *
  * This program is free software; you can redistribute it and/or modify it
  * under the terms and conditions of the GNU General Public License,
@@ -33,6 +33,7 @@
 #include <nvgpu/error_notifier.h>
 #include <nvgpu/barrier.h>
 #include <nvgpu/nvhost.h>
+#include <nvgpu/os_sched.h>
 
 #include "gk20a/gk20a.h"
 #include "gk20a/dbg_gpu_gk20a.h"
@@ -495,7 +496,8 @@ static int __gk20a_channel_open(struct gk20a *g,
 		goto fail_busy;
 	}
 	/* All the user space channel should be non privilege */
-	ch = gk20a_open_new_channel(g, runlist_id, false);
+	ch = gk20a_open_new_channel(g, runlist_id, false,
+				nvgpu_current_pid(g), nvgpu_current_tid(g));
 	gk20a_idle(g);
 	if (!ch) {
 		nvgpu_err(g,

drivers/gpu/nvgpu/common/linux/ioctl_tsg.c

@@ -24,6 +24,7 @@
 
 #include <nvgpu/kmem.h>
 #include <nvgpu/log.h>
+#include <nvgpu/os_sched.h>
 
 #include "gk20a/gk20a.h"
 #include "gk20a/tsg_gk20a.h"
@@ -370,7 +371,7 @@ int nvgpu_ioctl_tsg_open(struct gk20a *g, struct file *filp)
 		goto free_ref;
 	}
 
-	tsg = gk20a_tsg_open(g);
+	tsg = gk20a_tsg_open(g, nvgpu_current_pid(g));
 	if (!tsg) {
 		nvgpu_kfree(g, priv);
 		err = -ENOMEM;

drivers/gpu/nvgpu/gk20a/ce2_gk20a.c

@@ -1,7 +1,7 @@
 /*
  * GK20A Graphics Copy Engine  (gr host)
  *
- * Copyright (c) 2011-2017, NVIDIA CORPORATION.  All rights reserved.
+ * Copyright (c) 2011-2018, NVIDIA CORPORATION.  All rights reserved.
  *
  * Permission is hereby granted, free of charge, to any person obtaining a
  * copy of this software and associated documentation files (the "Software"),
@@ -24,6 +24,7 @@
 
 #include <nvgpu/kmem.h>
 #include <nvgpu/dma.h>
+#include <nvgpu/os_sched.h>
 
 #include "gk20a.h"
 
@@ -430,7 +431,7 @@ u32 gk20a_ce_create_context(struct gk20a *g,
 	ce_ctx->vm = g->mm.ce.vm;
 
 	/* allocate a tsg if needed */
-	ce_ctx->tsg = gk20a_tsg_open(g);
+	ce_ctx->tsg = gk20a_tsg_open(g, nvgpu_current_pid(g));
 	if (!ce_ctx->tsg) {
 		nvgpu_err(g, "ce: gk20a tsg not available");
 		err = -ENOMEM;
@@ -438,7 +439,8 @@ u32 gk20a_ce_create_context(struct gk20a *g,
 	}
 
 	/* always kernel client needs privileged channel */
-	ce_ctx->ch = gk20a_open_new_channel(g, runlist_id, true);
+	ce_ctx->ch = gk20a_open_new_channel(g, runlist_id, true,
+				nvgpu_current_pid(g), nvgpu_current_tid(g));
 	if (!ce_ctx->ch) {
 		nvgpu_err(g, "ce: gk20a channel not available");
 		err = -ENOMEM;

drivers/gpu/nvgpu/gk20a/channel_gk20a.c

@@ -615,7 +615,8 @@ void __gk20a_channel_kill(struct channel_gk20a *ch)
 
 struct channel_gk20a *gk20a_open_new_channel(struct gk20a *g,
 		s32 runlist_id,
-		bool is_privileged_channel)
+		bool is_privileged_channel,
+		pid_t pid, pid_t tid)
 {
 	struct fifo_gk20a *f = &g->fifo;
 	struct channel_gk20a *ch;
@@ -645,8 +646,8 @@ struct channel_gk20a *gk20a_open_new_channel(struct gk20a *g,
 	/* Channel privilege level */
 	ch->is_privileged_channel = is_privileged_channel;
 
-	ch->pid = nvgpu_current_tid(g);
-	ch->tgid = nvgpu_current_pid(g);  /* process granularity for FECS traces */
+	ch->pid = tid;
+	ch->tgid = pid;  /* process granularity for FECS traces */
 
 	if (g->ops.fifo.alloc_inst(g, ch)) {
 		ch->g = NULL;

drivers/gpu/nvgpu/gk20a/channel_gk20a.h

@@ -367,7 +367,8 @@ int gk20a_wait_channel_idle(struct channel_gk20a *ch);
 /* runlist_id -1 is synonym for ENGINE_GR_GK20A runlist id */
 struct channel_gk20a *gk20a_open_new_channel(struct gk20a *g,
 		s32 runlist_id,
-		bool is_privileged_channel);
+		bool is_privileged_channel,
+		pid_t pid, pid_t tid);
 
 int gk20a_channel_alloc_gpfifo(struct channel_gk20a *c,
 		struct nvgpu_gpfifo_args *gpfifo_args);

drivers/gpu/nvgpu/gk20a/tsg_gk20a.c

@@ -267,7 +267,7 @@ static struct tsg_gk20a *gk20a_tsg_acquire_unused_tsg(struct fifo_gk20a *f)
 	return tsg;
 }
 
-struct tsg_gk20a *gk20a_tsg_open(struct gk20a *g)
+struct tsg_gk20a *gk20a_tsg_open(struct gk20a *g, pid_t pid)
 {
 	struct tsg_gk20a *tsg;
 	int err;
@@ -286,7 +286,7 @@ struct tsg_gk20a *gk20a_tsg_open(struct gk20a *g)
 	tsg->timeslice_timeout = 0;
 	tsg->timeslice_scale = 0;
 	tsg->runlist_id = ~0;
-	tsg->tgid = nvgpu_current_pid(g);
+	tsg->tgid = pid;
 
 	if (g->ops.fifo.init_eng_method_buffers)
 		g->ops.fifo.init_eng_method_buffers(g, tsg);

drivers/gpu/nvgpu/gk20a/tsg_gk20a.h

@@ -33,7 +33,7 @@
 struct channel_gk20a;
 
 bool gk20a_is_channel_marked_as_tsg(struct channel_gk20a *ch);
-struct tsg_gk20a *gk20a_tsg_open(struct gk20a *g);
+struct tsg_gk20a *gk20a_tsg_open(struct gk20a *g, pid_t pid);
 void gk20a_tsg_release(struct nvgpu_ref *ref);
 
 int gk20a_init_tsg_support(struct gk20a *g, u32 tsgid);