gpu: nvgpu: Move gk20a_gr_alloc_global_ctx_buffers to gr.common

Move gk20a_gr_alloc_global_ctx_buffers from gr_gk20a.c to gr.c as
static function as gr_alloc_global_ctx_buffers. This function is
used locally by gr_init_setup_sw function.

Remove alloc_global_ctx_buffers hal function.

JIRA NVGPU-1885

Change-Id: I85f1ed85259cd564577b69af8cf01c1a2802004b
Signed-off-by: Vinod G <vinodg@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2093834
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>

drivers/gpu/nvgpu/common/gr/gr.c

@@ -34,6 +34,73 @@
 #include <nvgpu/gr/fs_state.h>
 #include <nvgpu/power_features/cg.h>
 
+static int gr_alloc_global_ctx_buffers(struct gk20a *g)
+{
+	struct gr_gk20a *gr = &g->gr;
+	int err;
+	u32 size;
+
+	nvgpu_log_fn(g, " ");
+
+	size = g->ops.gr.init.get_global_ctx_cb_buffer_size(g);
+	nvgpu_log_info(g, "cb_buffer_size : %d", size);
+
+	nvgpu_gr_global_ctx_set_size(gr->global_ctx_buffer,
+		NVGPU_GR_GLOBAL_CTX_CIRCULAR, size);
+	nvgpu_gr_global_ctx_set_size(gr->global_ctx_buffer,
+		NVGPU_GR_GLOBAL_CTX_CIRCULAR_VPR, size);
+
+	size = g->ops.gr.init.get_global_ctx_pagepool_buffer_size(g);
+	nvgpu_log_info(g, "pagepool_buffer_size : %d", size);
+
+	nvgpu_gr_global_ctx_set_size(gr->global_ctx_buffer,
+		NVGPU_GR_GLOBAL_CTX_PAGEPOOL, size);
+	nvgpu_gr_global_ctx_set_size(gr->global_ctx_buffer,
+		NVGPU_GR_GLOBAL_CTX_PAGEPOOL_VPR, size);
+
+	size = g->ops.gr.init.get_global_attr_cb_size(g,
+			nvgpu_gr_config_get_tpc_count(g->gr.config),
+			nvgpu_gr_config_get_max_tpc_count(g->gr.config));
+	nvgpu_log_info(g, "attr_buffer_size : %u", size);
+
+	nvgpu_gr_global_ctx_set_size(gr->global_ctx_buffer,
+		NVGPU_GR_GLOBAL_CTX_ATTRIBUTE, size);
+	nvgpu_gr_global_ctx_set_size(gr->global_ctx_buffer,
+		NVGPU_GR_GLOBAL_CTX_ATTRIBUTE_VPR, size);
+
+	nvgpu_log_info(g, "priv_access_map_size : %d",
+		   gr->ctx_vars.priv_access_map_size);
+
+	nvgpu_gr_global_ctx_set_size(gr->global_ctx_buffer,
+		NVGPU_GR_GLOBAL_CTX_PRIV_ACCESS_MAP,
+		gr->ctx_vars.priv_access_map_size);
+
+#ifdef CONFIG_GK20A_CTXSW_TRACE
+	nvgpu_log_info(g, "fecs_trace_buffer_size : %d",
+		   gr->ctx_vars.fecs_trace_buffer_size);
+
+	nvgpu_gr_global_ctx_set_size(gr->global_ctx_buffer,
+		NVGPU_GR_GLOBAL_CTX_FECS_TRACE_BUFFER,
+		gr->ctx_vars.fecs_trace_buffer_size);
+#endif
+
+	if (g->ops.gr.init.get_rtv_cb_size != NULL) {
+		size = g->ops.gr.init.get_rtv_cb_size(g);
+		nvgpu_log_info(g, "rtv_circular_buffer_size : %u", size);
+
+		nvgpu_gr_global_ctx_set_size(gr->global_ctx_buffer,
+			NVGPU_GR_GLOBAL_CTX_RTV_CIRCULAR_BUFFER, size);
+	}
+
+	err = nvgpu_gr_global_ctx_buffer_alloc(g, gr->global_ctx_buffer);
+	if (err != 0) {
+		return err;
+	}
+
+	nvgpu_log_fn(g, "done");
+	return 0;
+}
+
 u32 nvgpu_gr_gpc_offset(struct gk20a *g, u32 gpc)
 {
 	u32 gpc_stride = nvgpu_get_litter_value(g, GPU_LIT_GPC_STRIDE);
@@ -349,7 +416,7 @@ static int gr_init_setup_sw(struct gk20a *g)
 		goto clean_up;
 	}
 
-	err = g->ops.gr.alloc_global_ctx_buffers(g);
+	err = gr_alloc_global_ctx_buffers(g);
 	if (err != 0) {
 		goto clean_up;
 	}

drivers/gpu/nvgpu/common/vgpu/gp10b/vgpu_hal_gp10b.c

@@ -188,7 +188,6 @@ static const struct gpu_ops vgpu_gp10b_ops = {
 		.decode_priv_addr = gr_gk20a_decode_priv_addr,
 		.create_priv_addr_table = gr_gk20a_create_priv_addr_table,
 		.split_fbpa_broadcast_addr = gr_gk20a_split_fbpa_broadcast_addr,
-		.alloc_global_ctx_buffers = gr_gk20a_alloc_global_ctx_buffers,
 		.get_offset_in_gpccs_segment =
 			gr_gk20a_get_offset_in_gpccs_segment,
 		.set_debug_mode = gm20b_gr_set_debug_mode,

drivers/gpu/nvgpu/common/vgpu/gv11b/vgpu_hal_gv11b.c

@@ -220,7 +220,6 @@ static const struct gpu_ops vgpu_gv11b_ops = {
 		.decode_priv_addr = gr_gv11b_decode_priv_addr,
 		.create_priv_addr_table = gr_gv11b_create_priv_addr_table,
 		.split_fbpa_broadcast_addr = gr_gk20a_split_fbpa_broadcast_addr,
-		.alloc_global_ctx_buffers = gr_gk20a_alloc_global_ctx_buffers,
 		.get_nonpes_aware_tpc = gr_gv11b_get_nonpes_aware_tpc,
 		.get_offset_in_gpccs_segment =
 			gr_gk20a_get_offset_in_gpccs_segment,

drivers/gpu/nvgpu/gk20a/gr_gk20a.c

@@ -288,73 +288,6 @@ int gr_gk20a_update_hwpm_ctxsw_mode(struct gk20a *g,
 	return ret;
 }
 
-int gr_gk20a_alloc_global_ctx_buffers(struct gk20a *g)
-{
-	struct gr_gk20a *gr = &g->gr;
-	int err;
-	u32 size;
-
-	nvgpu_log_fn(g, " ");
-
-	size = g->ops.gr.init.get_global_ctx_cb_buffer_size(g);
-	nvgpu_log_info(g, "cb_buffer_size : %d", size);
-
-	nvgpu_gr_global_ctx_set_size(gr->global_ctx_buffer,
-		NVGPU_GR_GLOBAL_CTX_CIRCULAR, size);
-	nvgpu_gr_global_ctx_set_size(gr->global_ctx_buffer,
-		NVGPU_GR_GLOBAL_CTX_CIRCULAR_VPR, size);
-
-	size = g->ops.gr.init.get_global_ctx_pagepool_buffer_size(g);
-	nvgpu_log_info(g, "pagepool_buffer_size : %d", size);
-
-	nvgpu_gr_global_ctx_set_size(gr->global_ctx_buffer,
-		NVGPU_GR_GLOBAL_CTX_PAGEPOOL, size);
-	nvgpu_gr_global_ctx_set_size(gr->global_ctx_buffer,
-		NVGPU_GR_GLOBAL_CTX_PAGEPOOL_VPR, size);
-
-	size = g->ops.gr.init.get_global_attr_cb_size(g,
-			nvgpu_gr_config_get_tpc_count(g->gr.config),
-			nvgpu_gr_config_get_max_tpc_count(g->gr.config));
-	nvgpu_log_info(g, "attr_buffer_size : %u", size);
-
-	nvgpu_gr_global_ctx_set_size(gr->global_ctx_buffer,
-		NVGPU_GR_GLOBAL_CTX_ATTRIBUTE, size);
-	nvgpu_gr_global_ctx_set_size(gr->global_ctx_buffer,
-		NVGPU_GR_GLOBAL_CTX_ATTRIBUTE_VPR, size);
-
-	nvgpu_log_info(g, "priv_access_map_size : %d",
-		   gr->ctx_vars.priv_access_map_size);
-
-	nvgpu_gr_global_ctx_set_size(gr->global_ctx_buffer,
-		NVGPU_GR_GLOBAL_CTX_PRIV_ACCESS_MAP,
-		gr->ctx_vars.priv_access_map_size);
-
-#ifdef CONFIG_GK20A_CTXSW_TRACE
-	nvgpu_log_info(g, "fecs_trace_buffer_size : %d",
-		   gr->ctx_vars.fecs_trace_buffer_size);
-
-	nvgpu_gr_global_ctx_set_size(gr->global_ctx_buffer,
-		NVGPU_GR_GLOBAL_CTX_FECS_TRACE_BUFFER,
-		gr->ctx_vars.fecs_trace_buffer_size);
-#endif
-
-	if (g->ops.gr.init.get_rtv_cb_size != NULL) {
-		size = g->ops.gr.init.get_rtv_cb_size(g);
-		nvgpu_log_info(g, "rtv_circular_buffer_size : %u", size);
-
-		nvgpu_gr_global_ctx_set_size(gr->global_ctx_buffer,
-			NVGPU_GR_GLOBAL_CTX_RTV_CIRCULAR_BUFFER, size);
-	}
-
-	err = nvgpu_gr_global_ctx_buffer_alloc(g, gr->global_ctx_buffer);
-	if (err != 0) {
-		return err;
-	}
-
-	nvgpu_log_fn(g, "done");
-	return 0;
-}
-
 u32 gr_gk20a_get_patch_slots(struct gk20a *g)
 {
 	return PATCH_CTX_SLOTS_PER_PAGE;

drivers/gpu/nvgpu/gk20a/gr_gk20a.h

@@ -359,8 +359,6 @@ void gk20a_gr_get_ovr_perf_regs(struct gk20a *g, u32 *num_ovr_perf_regs,
 					       u32 **ovr_perf_regs);
 u32 gr_gk20a_get_patch_slots(struct gk20a *g);
 
-int gr_gk20a_alloc_global_ctx_buffers(struct gk20a *g);
-
 int gk20a_init_sw_bundle(struct gk20a *g);
 int gr_gk20a_decode_priv_addr(struct gk20a *g, u32 addr,
 	enum ctxsw_addr_type *addr_type,

drivers/gpu/nvgpu/gm20b/hal_gm20b.c

@@ -307,7 +307,6 @@ static const struct gpu_ops gm20b_ops = {
 		.decode_priv_addr = gr_gk20a_decode_priv_addr,
 		.create_priv_addr_table = gr_gk20a_create_priv_addr_table,
 		.split_fbpa_broadcast_addr = gr_gk20a_split_fbpa_broadcast_addr,
-		.alloc_global_ctx_buffers = gr_gk20a_alloc_global_ctx_buffers,
 		.get_offset_in_gpccs_segment =
 			gr_gk20a_get_offset_in_gpccs_segment,
 		.set_debug_mode = gm20b_gr_set_debug_mode,

drivers/gpu/nvgpu/gp10b/hal_gp10b.c

@@ -344,7 +344,6 @@ static const struct gpu_ops gp10b_ops = {
 		.decode_priv_addr = gr_gk20a_decode_priv_addr,
 		.create_priv_addr_table = gr_gk20a_create_priv_addr_table,
 		.split_fbpa_broadcast_addr = gr_gk20a_split_fbpa_broadcast_addr,
-		.alloc_global_ctx_buffers = gr_gk20a_alloc_global_ctx_buffers,
 		.get_offset_in_gpccs_segment =
 			gr_gk20a_get_offset_in_gpccs_segment,
 		.set_debug_mode = gm20b_gr_set_debug_mode,

drivers/gpu/nvgpu/gv100/hal_gv100.c

@@ -464,7 +464,6 @@ static const struct gpu_ops gv100_ops = {
 		.decode_priv_addr = gr_gv11b_decode_priv_addr,
 		.create_priv_addr_table = gr_gv11b_create_priv_addr_table,
 		.split_fbpa_broadcast_addr = gr_gv100_split_fbpa_broadcast_addr,
-		.alloc_global_ctx_buffers = gr_gk20a_alloc_global_ctx_buffers,
 		.get_nonpes_aware_tpc = gr_gv11b_get_nonpes_aware_tpc,
 		.get_offset_in_gpccs_segment =
 			gr_gk20a_get_offset_in_gpccs_segment,

drivers/gpu/nvgpu/gv11b/hal_gv11b.c

@@ -423,7 +423,6 @@ static const struct gpu_ops gv11b_ops = {
 		.decode_priv_addr = gr_gv11b_decode_priv_addr,
 		.create_priv_addr_table = gr_gv11b_create_priv_addr_table,
 		.split_fbpa_broadcast_addr = gr_gk20a_split_fbpa_broadcast_addr,
-		.alloc_global_ctx_buffers = gr_gk20a_alloc_global_ctx_buffers,
 		.get_nonpes_aware_tpc = gr_gv11b_get_nonpes_aware_tpc,
 		.get_offset_in_gpccs_segment =
 			gr_gk20a_get_offset_in_gpccs_segment,

drivers/gpu/nvgpu/include/nvgpu/gk20a.h

@@ -427,7 +427,6 @@ struct gpu_ops {
 					u32 num_fbpas,
 					u32 *priv_addr_table,
 					u32 *priv_addr_table_index);
-		int (*alloc_global_ctx_buffers)(struct gk20a *g);
 		u32 (*get_nonpes_aware_tpc)(struct gk20a *g, u32 gpc, u32 tpc);
 		int (*get_offset_in_gpccs_segment)(struct gk20a *g,
 			enum ctxsw_addr_type addr_type, u32 num_tpcs,

drivers/gpu/nvgpu/tu104/hal_tu104.c

@@ -489,7 +489,6 @@ static const struct gpu_ops tu104_ops = {
 		.decode_priv_addr = gr_gv11b_decode_priv_addr,
 		.create_priv_addr_table = gr_gv11b_create_priv_addr_table,
 		.split_fbpa_broadcast_addr = gr_gv100_split_fbpa_broadcast_addr,
-		.alloc_global_ctx_buffers = gr_gk20a_alloc_global_ctx_buffers,
 		.get_nonpes_aware_tpc = gr_gv11b_get_nonpes_aware_tpc,
 		.get_offset_in_gpccs_segment =
 			gr_tu104_get_offset_in_gpccs_segment,