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gpu: nvgpu: add HAL for reading ccsr_channel

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Refactor read accesses to the ccsr_channel register for channel state to
be done via a channel HAL op for all chips. A new op called read_state
is added for this; information needed by other units is collected in a
new struct nvgpu_channel_hw_state.

Jira NVGPU-1307

Change-Id: Iff9385c08e17ac086d97f5771a54b56b2727e3c4
Signed-off-by: Konsta Holtta <kholtta@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2017266
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
This commit is contained in:
Konsta Holtta
2019-02-12 13:05:18 +02:00
committed by mobile promotions
parent 335e4f1839
commit cd4b2f642c
14 changed files with 92 additions and 83 deletions
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11
drivers/gpu/nvgpu/include/nvgpu/fifo.h
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@@ -35,4 +35,13 @@
#define RC_TYPE_FORCE_RESET 7U
#define RC_TYPE_SCHED_ERR 8U
#endif /* NVGPU_FIFO_COMMON_H */
struct nvgpu_channel_hw_state {
bool enabled;
bool next;
bool ctx_reload;
bool busy;
bool pending_acquire;
const char *status_string;
};
#endif /* NVGPU_FIFO_COMMON_H */