diff --git a/drivers/gpu/nvgpu/common/gr/gr.c b/drivers/gpu/nvgpu/common/gr/gr.c
index ef67c54e2..b4a3d64b0 100644
--- a/drivers/gpu/nvgpu/common/gr/gr.c
+++ b/drivers/gpu/nvgpu/common/gr/gr.c
@@ -513,11 +513,6 @@ static int gr_init_setup_sw(struct gk20a *g)
 		goto clean_up;
 	}
 
-	err = gr_init_config(g, gr);
-	if (err != 0) {
-		goto clean_up;
-	}
-
 #ifdef CONFIG_NVGPU_DEBUGGER
 	err = nvgpu_gr_hwpm_map_init(g, &g->gr->hwpm_map,
 			nvgpu_gr_falcon_get_pm_ctxsw_image_size(g->gr->falcon));
@@ -778,6 +773,27 @@ int nvgpu_gr_init_support(struct gk20a *g)
 
 	g->gr->initialized = false;
 
+	/* This is prerequisite for calling sm_id_config_early hal. */
+	if (!g->gr->sw_ready) {
+		err = gr_init_config(g, g->gr);
+		if (err != 0) {
+			return err;
+		}
+	}
+
+#if defined(CONFIG_NVGPU_NEXT)
+	/*
+	 * Move sm id programming before loading ctxsw and gpccs firmwares. This
+	 * is the actual sequence expected by ctxsw ucode.
+	 */
+	if (g->ops.gr.init.sm_id_config_early != NULL) {
+		err = g->ops.gr.init.sm_id_config_early(g, g->gr->config);
+		if (err != 0) {
+			return err;
+		}
+	}
+#endif
+
 	err = nvgpu_gr_falcon_init_ctxsw(g, g->gr->falcon);
 	if (err != 0) {
 		gr_intr_report_ctxsw_error(g, GPU_FECS_CTXSW_INIT_ERROR, 0, 0);
diff --git a/drivers/gpu/nvgpu/include/nvgpu/gr/fs_state.h b/drivers/gpu/nvgpu/include/nvgpu/gr/fs_state.h
index 6e643d787..719342e83 100644
--- a/drivers/gpu/nvgpu/include/nvgpu/gr/fs_state.h
+++ b/drivers/gpu/nvgpu/include/nvgpu/gr/fs_state.h
@@ -51,5 +51,10 @@ struct nvgpu_gr_config;
  *         structure.
  */
 int nvgpu_gr_fs_state_init(struct gk20a *g, struct nvgpu_gr_config *config);
+/** @cond DOXYGEN_SHOULD_SKIP_THIS */
+#if defined(CONFIG_NVGPU_NEXT)
+#include "include/nvgpu/gr/nvgpu_next_fs_state.h"
+#endif
+/** @endcond DOXYGEN_SHOULD_SKIP_THIS */
 
 #endif /* NVGPU_GR_FS_STATE_H */