From cdeaf09b2b4ed61f4051263c9e2506bbdda8a969 Mon Sep 17 00:00:00 2001 From: Sagar Kamble Date: Fri, 3 Jan 2020 11:25:44 +0530 Subject: [PATCH] gpu: nvgpu: falcon: whitelist MISRA 11.3 violations Whitelist 2 MISRA Rule 11.3 violations in falcon that were approved as deviations in TID-415. Check for alignment is added before casting the u8 pointer to u32 pointer and unaligned source buffers are handled byte by byte. JIRA NVGPU-4812 JIRA TID-415 Change-Id: Ib7aaced0714029392c9d94468a74f11f182c9d74 Signed-off-by: Sagar Kamble Reviewed-on: https://git-master.nvidia.com/r/2272752 Reviewed-by: svc-mobile-coverity Reviewed-by: svc-mobile-misra Reviewed-by: svc-mobile-cert GVS: Gerrit_Virtual_Submit Reviewed-by: Vaibhav Kachore Reviewed-by: mobile promotions Tested-by: mobile promotions --- drivers/gpu/nvgpu/hal/falcon/falcon_gk20a_fusa.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/gpu/nvgpu/hal/falcon/falcon_gk20a_fusa.c b/drivers/gpu/nvgpu/hal/falcon/falcon_gk20a_fusa.c index 9ecff38a3..dc2c68cb1 100644 --- a/drivers/gpu/nvgpu/hal/falcon/falcon_gk20a_fusa.c +++ b/drivers/gpu/nvgpu/hal/falcon/falcon_gk20a_fusa.c @@ -188,6 +188,7 @@ int gk20a_falcon_copy_to_dmem(struct nvgpu_falcon *flcn, dst | falcon_falcon_dmemc_aincw_f(1)); if (likely(nvgpu_mem_is_word_aligned(flcn->g, src))) { +NVGPU_COV_WHITELIST(deviate, NVGPU_MISRA(Rule, 11_3), "TID-415") src_u32 = (u32 *)src; for (i = 0; i < words; i++) { @@ -300,6 +301,7 @@ int gk20a_falcon_copy_to_imem(struct nvgpu_falcon *flcn, u32 dst, falcon_falcon_imemc_secure_f(sec ? 1U : 0U)); if (likely(nvgpu_mem_is_word_aligned(flcn->g, src))) { +NVGPU_COV_WHITELIST(deviate, NVGPU_MISRA(Rule, 11_3), "TID-415") src_u32 = (u32 *)src; for (i = 0U; i < words; i++) {