From ce22f1efb1d985a8e5f2794803dbd1ae7ccf8e39 Mon Sep 17 00:00:00 2001 From: Rajesh Devaraj Date: Sun, 16 Apr 2023 07:19:09 +0000 Subject: [PATCH] gpu: nvgpu: add functions to query vgpc config This patch adds the following functions which can be used to set/query skyline configuration: nvgpu_gr_config_set_singleton_mask nvgpu_gr_config_get_singleton_mask nvgpu_gr_config_set_num_singletons nvgpu_gr_config_get_num_singletons nvgpu_gr_config_set_num_tpc_in_skyline nvgpu_gr_config_get_num_tpc_in_skyline nvgpu_gr_config_set_gpc_skyline nvgpu_gr_config_get_gpc_skyline nvgpu_gr_config_set_virtual_gpc_id nvgpu_gr_config_get_virtual_gpc_id nvgpu_gr_config_set_sm_info_virtual_gpc_index nvgpu_gr_config_get_sm_info_virtual_gpc_index JIRA NVGPU-9897 Change-Id: If80e19f709472d74b42cb9c4b47dc4ce4f9a54dc Signed-off-by: Rajesh Devaraj Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2888783 Tested-by: mobile promotions Reviewed-by: mobile promotions --- drivers/gpu/nvgpu/common/gr/gr_config.c | 97 ++++++++++- drivers/gpu/nvgpu/common/gr/gr_config_priv.h | 24 +++ drivers/gpu/nvgpu/include/nvgpu/gk20a.h | 2 + drivers/gpu/nvgpu/include/nvgpu/gr/config.h | 172 ++++++++++++++++++- 4 files changed, 291 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/nvgpu/common/gr/gr_config.c b/drivers/gpu/nvgpu/common/gr/gr_config.c index dbd536576..c86bba610 100644 --- a/drivers/gpu/nvgpu/common/gr/gr_config.c +++ b/drivers/gpu/nvgpu/common/gr/gr_config.c @@ -342,6 +342,10 @@ static void gr_config_log_info(struct gk20a *g, nvgpu_log(g, gpu_dbg_info | gpu_dbg_gr, "gpc_tpc_mask[%d] : 0x%x", gpc_index, config->gpc_tpc_mask[gpc_index]); } + for (gpc_index = 0; gpc_index < config->max_gpc_count; gpc_index++) { + nvgpu_log(g, gpu_dbg_info | gpu_dbg_gr, "gpc_skyline[%d] : 0x%x", + gpc_index, config->gpc_skyline[gpc_index]); + } #ifdef CONFIG_NVGPU_GRAPHICS for (gpc_index = 0; gpc_index < config->gpc_count; gpc_index++) { nvgpu_log(g, gpu_dbg_info | gpu_dbg_gr, "gpc_zcb_count[%d] : %d", @@ -391,8 +395,8 @@ static void gr_config_set_gpc_mask(struct gk20a *g, static bool gr_config_alloc_valid(struct nvgpu_gr_config *config) { if ((config->gpc_tpc_count == NULL) || (config->gpc_tpc_mask == NULL) || - (config->gpc_ppc_count == NULL) || - (config->gpc_skip_mask == NULL)) { + (config->gpc_ppc_count == NULL) || (config->gpc_skyline == NULL) || + (config->gpc_skip_mask == NULL) || (config->gpc_info == NULL)) { return false; } @@ -409,7 +413,9 @@ static bool gr_config_alloc_valid(struct nvgpu_gr_config *config) static void gr_config_free_mem(struct gk20a *g, struct nvgpu_gr_config *config) { - u32 pes_index; + u32 pes_index, i; + size_t max_gpc_cnt = nvgpu_safe_mult_u64((size_t)config->max_gpc_count, + sizeof(u32)); for (pes_index = 0U; pes_index < config->pe_count_per_gpc; pes_index++) { nvgpu_kfree(g, config->pes_tpc_count[pes_index]); @@ -424,6 +430,11 @@ static void gr_config_free_mem(struct gk20a *g, nvgpu_kfree(g, config->gpc_tpc_mask); nvgpu_kfree(g, config->gpc_tpc_count); nvgpu_kfree(g, config->gpc_tpc_mask_physical); + nvgpu_kfree(g, config->gpc_skyline); + for (i = 0; i < max_gpc_cnt; i++) { + nvgpu_kfree(g, config->gpc_info[i].virtual_gpc_info); + } + nvgpu_kfree(g, config->gpc_info); } static bool gr_config_alloc_struct_mem(struct gk20a *g, @@ -434,6 +445,7 @@ static bool gr_config_alloc_struct_mem(struct gk20a *g, size_t sm_info_size; size_t gpc_size, sm_size, max_gpc_cnt; size_t pd_tbl_size; + u32 i = 0; total_tpc_cnt = nvgpu_safe_mult_u32(config->gpc_count, config->max_tpc_per_gpc_count); @@ -465,6 +477,14 @@ static bool gr_config_alloc_struct_mem(struct gk20a *g, config->gpc_tpc_count = nvgpu_kzalloc(g, gpc_size); config->gpc_tpc_mask = nvgpu_kzalloc(g, max_gpc_cnt); config->gpc_tpc_mask_physical = nvgpu_kzalloc(g, max_gpc_cnt); + config->gpc_skyline = nvgpu_kzalloc(g, max_gpc_cnt); + config->gpc_info = nvgpu_kzalloc(g, + nvgpu_safe_mult_u64(max_gpc_cnt, + sizeof(struct nvgpu_gpc_info))); + for (i = 0; i < max_gpc_cnt; i++) { + config->gpc_info[i].virtual_gpc_info = + nvgpu_kzalloc(g, config->max_gpc_count * sizeof(u32)); + } #ifdef CONFIG_NVGPU_GRAPHICS if (!nvgpu_is_enabled(g, NVGPU_SUPPORT_MIG)) { config->max_zcull_per_gpc_count = nvgpu_get_litter_value(g, @@ -1124,6 +1144,66 @@ u32 nvgpu_gr_config_get_gpc_mask(struct nvgpu_gr_config *config) return config->gpc_mask; } +void nvgpu_gr_config_set_singleton_mask(struct nvgpu_gr_config *config, u32 val) +{ + config->singleton_mask = val; +} + +u32 nvgpu_gr_config_get_singleton_mask(struct nvgpu_gr_config *config) +{ + return config->singleton_mask; +} + +void nvgpu_gr_config_set_num_singletons(struct nvgpu_gr_config *config, u32 val) +{ + config->num_singletons = val; +} + +u32 nvgpu_gr_config_get_num_singletons(struct nvgpu_gr_config *config) +{ + return config->num_singletons; +} + +void nvgpu_gr_config_set_num_tpc_in_skyline(struct nvgpu_gr_config *config, u32 val) +{ + config->num_tpc_in_skyline = val; +} + +u32 nvgpu_gr_config_get_num_tpc_in_skyline(struct nvgpu_gr_config *config) +{ + return config->num_tpc_in_skyline; +} + +void nvgpu_gr_config_set_virtual_gpc_id(struct nvgpu_gr_config *config, + struct tpc_vgpc_table *vgpc_table, u32 global_tpc_id, + u32 gpc_index, u32 tpc_index) +{ + nvgpu_assert(gpc_index < nvgpu_gr_config_get_max_gpc_count(config)); + config->gpc_info[vgpc_table[global_tpc_id].gpc_id].virtual_gpc_info[tpc_index] + = gpc_index; +} + +u32 nvgpu_gr_config_get_virtual_gpc_id(struct nvgpu_gr_config *config, + u32 gpc_index, u32 vtpc_index) +{ + nvgpu_assert(gpc_index < nvgpu_gr_config_get_max_gpc_count(config)); + return config->gpc_info[gpc_index].virtual_gpc_info[vtpc_index]; +} + +void nvgpu_gr_config_set_gpc_skyline(struct nvgpu_gr_config *config, + u32 gpc_index, u32 val) +{ + nvgpu_assert(gpc_index < nvgpu_gr_config_get_max_gpc_count(config)); + config->gpc_skyline[gpc_index] = val; +} + +u32 nvgpu_gr_config_get_gpc_skyline(struct nvgpu_gr_config *config, + u32 gpc_index) +{ + nvgpu_assert(gpc_index < nvgpu_gr_config_get_max_gpc_count(config)); + return config->gpc_skyline[gpc_index]; +} + u32 nvgpu_gr_config_get_no_of_sm(struct nvgpu_gr_config *config) { return config->no_of_sm; @@ -1194,3 +1274,14 @@ void nvgpu_gr_config_set_sm_info_sm_index(struct nvgpu_sm_info *sm_info, { sm_info->sm_index = sm_index; } + +u32 nvgpu_gr_config_get_sm_info_virtual_gpc_index(struct nvgpu_sm_info *sm_info) +{ + return sm_info->virtual_gpc_index; +} + +void nvgpu_gr_config_set_sm_info_virtual_gpc_index(struct nvgpu_sm_info *sm_info, + u32 virtual_gpc_index) +{ + sm_info->virtual_gpc_index = virtual_gpc_index; +} diff --git a/drivers/gpu/nvgpu/common/gr/gr_config_priv.h b/drivers/gpu/nvgpu/common/gr/gr_config_priv.h index 36e01aa80..df371da7a 100644 --- a/drivers/gpu/nvgpu/common/gr/gr_config_priv.h +++ b/drivers/gpu/nvgpu/common/gr/gr_config_priv.h @@ -30,6 +30,8 @@ */ #define GK20A_GR_MAX_PES_PER_GPC 3U +#define ILLEGAL_VGPC 0xFFU + struct gk20a; /** @@ -55,6 +57,15 @@ struct nvgpu_sm_info { * Global TPC index for SM. */ u32 global_tpc_index; + + /** + * Virtual GPC index for SM. + */ + u32 virtual_gpc_index; +}; + +struct nvgpu_gpc_info { + u32 *virtual_gpc_info; }; /** @@ -208,6 +219,19 @@ struct nvgpu_gr_config { u32 map_tile_count; u32 map_row_offset; #endif + + u32 singleton_mask; + u32 num_singletons; + u32 num_tpc_in_skyline; + u32 *gpc_skyline; + struct nvgpu_gpc_info *gpc_info; +}; + +struct tpc_vgpc_table { + u32 gpc_id; + u32 tpc_id; + u32 global_tpc_id; + u32 virtual_gpc_id; }; #endif /* NVGPU_GR_CONFIG_PRIV_H */ diff --git a/drivers/gpu/nvgpu/include/nvgpu/gk20a.h b/drivers/gpu/nvgpu/include/nvgpu/gk20a.h index d81bf011e..12b186a3e 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/gk20a.h +++ b/drivers/gpu/nvgpu/include/nvgpu/gk20a.h @@ -310,6 +310,8 @@ struct railgate_stats { #define GPU_LIT_NVDEC_CLASS 60 /** NVJPG class. */ #define GPU_LIT_NVJPG_CLASS 61 +/** Number of singleton gpcs. */ +#define GPU_LIT_NUM_SINGLETON_GPCS 62 /** Macro to get litter values corresponding to the litter defines. */ #define nvgpu_get_litter_value(g, v) ((g)->ops.get_litter_value((g), v)) diff --git a/drivers/gpu/nvgpu/include/nvgpu/gr/config.h b/drivers/gpu/nvgpu/include/nvgpu/gr/config.h index 328d5302b..d8750c886 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/gr/config.h +++ b/drivers/gpu/nvgpu/include/nvgpu/gr/config.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2019-2022, NVIDIA CORPORATION. All rights reserved. + * Copyright (c) 2019-2023, NVIDIA CORPORATION. All rights reserved. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), @@ -33,6 +33,7 @@ struct gk20a; struct nvgpu_sm_info; struct nvgpu_gr_config; +struct tpc_vgpc_table; /* * Number of bits represents a PES Mask. @@ -388,6 +389,154 @@ u32 nvgpu_gr_config_get_pes_tpc_mask(struct nvgpu_gr_config *config, */ u32 nvgpu_gr_config_get_gpc_mask(struct nvgpu_gr_config *config); +/** + * @brief Set singleton mask. + * + * @param config [in] Pointer to GR configuration struct. + * @param val [in] Mask value to be set. + * + * This function sets the singleton mask in #nvgpu_gr_config struct. + */ +void nvgpu_gr_config_set_singleton_mask(struct nvgpu_gr_config *config, + u32 val); + +/** + * @brief Get singleton mask. + * + * @param config [in] Pointer to GR configuration struct. + * + * This function returns the singleton mask of enabled singleton TPCs. + * + * @return mask of enabled singleton TPCs. + */ +u32 nvgpu_gr_config_get_singleton_mask(struct nvgpu_gr_config *config); + +/** + * @brief Set number of singletons. + * + * @param config [in] Pointer to GR configuration struct. + * @param val [in] Value to be set. + * + * The TPCs which are not part of virtual GPCs are called singleton TPCs. + * + * This function sets the number of singletons in #nvgpu_gr_config struct. + */ +void nvgpu_gr_config_set_num_singletons(struct nvgpu_gr_config *config, + u32 val); + +/** + * @brief Get number of singletons. + * + * @param config [in] Pointer to GR configuration struct. + * + * This function sets the number of singletons in #nvgpu_gr_config struct. + */ +u32 nvgpu_gr_config_get_num_singletons(struct nvgpu_gr_config *config); + +/** + * @brief Set number of TPCs in skyline. + * + * @param config [in] Pointer to GR configuration struct. + * @param val [in] Skyline value to be set. + * + * The skyline defines how many TPCs are in each virtual GPC. + * This function sets the number of TPCs in skyline in #nvgpu_gr_config struct. + * GPC index must be less than value returned by + * #nvgpu_gr_config_get_gpc_count(), otherwise an assert is raised. + */ +void nvgpu_gr_config_set_num_tpc_in_skyline(struct nvgpu_gr_config *config, + u32 val); + +/** + * @brief Get number of TPCs in skyline. + * + * @param config [in] Pointer to GR configuration struct. + * + * The skyline defines how many TPCs are in each virtual GPC. + * This function returns the number of TPCs in skyline in #nvgpu_gr_config struct. + * GPC index must be less than value returned by + * #nvgpu_gr_config_get_gpc_count(), otherwise an assert is raised. + * + * @return the number of TPCs in skyline. + */ +u32 nvgpu_gr_config_get_num_tpc_in_skyline(struct nvgpu_gr_config *config); + +/** + * @brief Set skyline for a given GPC. + * + * @param config [in] Pointer to GR configuration struct. + * @param gpc_index [in] Valid GPC index. + * @param val [in] Skyline value to be set. + * + * The skyline defines how many TPCs are in each virtual GPC. + * This function sets the skyline in #nvgpu_gr_config struct + * for given GPC index. + * GPC index must be less than value returned by + * #nvgpu_gr_config_get_gpc_count(), otherwise an assert is raised. + */ +void nvgpu_gr_config_set_gpc_skyline(struct nvgpu_gr_config *config, + u32 gpc_index, u32 val); + +/** + * @brief Get skyline for a given GPC. + * + * @param config [in] Pointer to GR configuration struct. + * @param gpc_index [in] Valid GPC index. + * + * The skyline defines how many TPCs are in each virtual GPC. + * This function returns the skyline in #nvgpu_gr_config struct + * for given GPC index. + * GPC index must be less than value returned by + * #nvgpu_gr_config_get_gpc_count(), otherwise an assert is raised. + * + * @return number of TPCs in skyline GPC. + */ +u32 nvgpu_gr_config_get_gpc_skyline(struct nvgpu_gr_config *config, + u32 gpc_index); + +/** + * @brief Set virtual GPC ID for a given GPC. + * + * @param config [in] Pointer to GR configuration struct. + * @param vgpc_table [in] Pointer to Virtual GPC table. + * @param global_tpc_id [in] Global TPC index. + * @param gpc_index [in] Valid GPC index. + * @param tpc_index [in] Valid TPC index. + * @param val [in] Mask value to be set. + * + * The virtual GPCs are numbered based on the number of non-floorswept + * TPCs that exist per GPC. They are numbered from largest to smallest + * TPC count, independent of which GPCs support graphics. + * + * This function sets the virtual GPC table in #tpc_vgpc_table struct + * for given GPC, TPC indices. + * GPC index must be less than value returned by + * #nvgpu_gr_config_get_gpc_count(), otherwise an assert is raised. + */ +void nvgpu_gr_config_set_virtual_gpc_id(struct nvgpu_gr_config *config, + struct tpc_vgpc_table *vgpc_table, u32 global_tpc_id, + u32 gpc_index, u32 tpc_index); + +/** + * @brief Get virtual GPC ID for a given GPC. + * + * @param config [in] Pointer to GR configuration struct. + * @param gpc_index [in] Valid GPC index. + * @param vtpc_index [in] Valid TPC index. + * + * The virtual GPCs are numbered based on the number of non-floorswept + * TPCs that exist per GPC. They are numbered from largest to smallest + * TPC count, independent of which GPCs support graphics. + * + * This function returns the virtual GPC index of a given TPC. + * GPC index must be less than value returned by + * #nvgpu_gr_config_get_gpc_count(), otherwise an assert is raised. + * + * @return virtual GPC ID for a given GPC. + */ +u32 nvgpu_gr_config_get_virtual_gpc_id(struct nvgpu_gr_config *config, + u32 gpc_index, u32 vtpc_index); + /** * @brief Get number of SMs. * @@ -520,6 +669,27 @@ u32 nvgpu_gr_config_get_sm_info_global_tpc_index(struct nvgpu_sm_info *sm_info); void nvgpu_gr_config_set_sm_info_global_tpc_index(struct nvgpu_sm_info *sm_info, u32 global_tpc_index); +/** + * @brief Set virtual GPC index of SM. + * + * @param sm_info [in] Pointer to SM information struct. + * @param virtual_gpc_index [in] Virtual GPC index to be set. + * + * This function sets virtual GPC index of SM into given #nvgpu_sm_info struct. + */ +void nvgpu_gr_config_set_sm_info_virtual_gpc_index(struct nvgpu_sm_info *sm_info, + u32 virtual_gpc_index); + +/** + * @brief Get virtual GPC index of SM. + * + * @param sm_info [in] Pointer to SM information struct. + * @param virtual_gpc_index [in] Virtual GPC index to be set. + * + * This function returns virtual GPC index of SM from given #nvgpu_sm_info struct. + */ +u32 nvgpu_gr_config_get_sm_info_virtual_gpc_index(struct nvgpu_sm_info *sm_info); + /** * @brief Get index of SM within TPC. *