From ce7d589a4d4cc46352d3de8e9604ab0671ddce13 Mon Sep 17 00:00:00 2001 From: Mahantesh Kumbar Date: Sun, 5 Dec 2021 19:49:16 +0000 Subject: [PATCH] gpu: nvgpu: ga10b: add PMU interrupt check hal -GA10B PMU IRQ registers are not accessible when NVRISCV PRIV lockdown is engaged, so need to skip accessing IRQ registers. NVGPU-7061 Change-Id: If5233e502a9bef838839376c412582e08d729a99 Signed-off-by: Mahantesh Kumbar Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2636964 Tested-by: mobile promotions Reviewed-by: mobile promotions --- drivers/gpu/nvgpu/hal/init/hal_ga10b.c | 2 +- drivers/gpu/nvgpu/hal/pmu/pmu_ga10b.c | 18 ++++++++++++++++++ drivers/gpu/nvgpu/hal/pmu/pmu_ga10b.h | 3 +++ 3 files changed, 22 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/nvgpu/hal/init/hal_ga10b.c b/drivers/gpu/nvgpu/hal/init/hal_ga10b.c index 7628ff016..cb3c5bff0 100644 --- a/drivers/gpu/nvgpu/hal/init/hal_ga10b.c +++ b/drivers/gpu/nvgpu/hal/init/hal_ga10b.c @@ -1329,7 +1329,7 @@ static const struct gops_pmu ga10b_ops_pmu = { .pmu_pstate_pmu_setup = nvgpu_pmu_pstate_pmu_setup, .pmu_destroy = nvgpu_pmu_destroy, /* ISR */ - .pmu_is_interrupted = gk20a_pmu_is_interrupted, + .pmu_is_interrupted = ga10b_pmu_is_interrupted, .handle_swgen1_irq = ga10b_pmu_handle_swgen1_irq, /* queue */ .pmu_get_queue_head = gv11b_pmu_queue_head_r, diff --git a/drivers/gpu/nvgpu/hal/pmu/pmu_ga10b.c b/drivers/gpu/nvgpu/hal/pmu/pmu_ga10b.c index b14c02f60..1d5ccc8ba 100644 --- a/drivers/gpu/nvgpu/hal/pmu/pmu_ga10b.c +++ b/drivers/gpu/nvgpu/hal/pmu/pmu_ga10b.c @@ -28,6 +28,7 @@ #include #include +#include "pmu_gk20a.h" #include "pmu_gv11b.h" #include "pmu_ga10b.h" @@ -363,6 +364,23 @@ void ga10b_pmu_handle_swgen1_irq(struct gk20a *g, u32 intr) #endif } +/* + * GA10B PMU IRQ registers are not accessible when NVRISCV PRIV + * lockdown is engaged, so need to skip accessing IRQ registers. + */ +#ifdef CONFIG_NVGPU_LS_PMU +bool ga10b_pmu_is_interrupted(struct nvgpu_pmu *pmu) +{ + struct gk20a *g = pmu->g; + + if (!g->ops.falcon.is_priv_lockdown(pmu->flcn)) { + return gk20a_pmu_is_interrupted(pmu); + } + + return false; +} +#endif + /* * GA10B PMU IRQ registers are not accessible when NVRISCV PRIV lockdown is * engaged, so need to skip modifying/configuring IRQ registers. diff --git a/drivers/gpu/nvgpu/hal/pmu/pmu_ga10b.h b/drivers/gpu/nvgpu/hal/pmu/pmu_ga10b.h index 68deb9c01..246123a2d 100644 --- a/drivers/gpu/nvgpu/hal/pmu/pmu_ga10b.h +++ b/drivers/gpu/nvgpu/hal/pmu/pmu_ga10b.h @@ -53,5 +53,8 @@ void ga10b_pmu_reset_idle_counter(struct gk20a *g, u32 counter_id); u32 ga10b_pmu_get_irqmask(struct gk20a *g); bool ga10b_pmu_is_debug_mode_en(struct gk20a *g); void ga10b_pmu_handle_swgen1_irq(struct gk20a *g, u32 intr); +#ifdef CONFIG_NVGPU_LS_PMU +bool ga10b_pmu_is_interrupted(struct nvgpu_pmu *pmu); +#endif void ga10b_pmu_enable_irq(struct nvgpu_pmu *pmu, bool enable); #endif /* NVGPU_PMU_GA10B_H */