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gpu: nvgpu: gp10b: fix swdx_rm_spill size and pointer

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Fixed incorrectly encoded pointer and size.

bug 1525327
bug 1581799

Change-Id: Ie6e94e47c3b11e9d9aa63a70b61e6e89f69e971b
Signed-off-by: Kirill Artamonov <kartamonov@nvidia.com>
Reviewed-on: http://git-master/r/713209
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
This commit is contained in:
Kirill Artamonov
2015-03-03 17:29:19 +02:00
committed by Deepak Nibade
parent 8fe7abebbb
commit ce85eae72a
1 changed files with 3 additions and 2 deletions
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5
drivers/gpu/nvgpu/gp10b/gr_gp10b.c
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@@ -664,8 +664,9 @@ static void gr_gp10b_update_ctxsw_preemption_mode(struct gk20a *g,
addr = (u64_lo32(gr_ctx->t18x.spill_ctxsw_buffer.gpu_va) >> addr = (u64_lo32(gr_ctx->t18x.spill_ctxsw_buffer.gpu_va) >>
gr_gpc0_swdx_rm_spill_buffer_addr_39_8_align_bits_v()) | gr_gpc0_swdx_rm_spill_buffer_addr_39_8_align_bits_v()) |
(u64_hi32(gr_ctx->t18x.pagepool_ctxsw_buffer.gpu_va) << (u64_hi32(gr_ctx->t18x.spill_ctxsw_buffer.gpu_va) <<
(32 - gr_gpc0_swdx_rm_spill_buffer_addr_39_8_align_bits_v())); (32 - gr_gpc0_swdx_rm_spill_buffer_addr_39_8_align_bits_v()));
size = gr_ctx->t18x.spill_ctxsw_buffer.size;
gr_gk20a_ctx_patch_write(g, ch_ctx, gr_gk20a_ctx_patch_write(g, ch_ctx,
gr_gpc0_swdx_rm_spill_buffer_addr_r(), gr_gpc0_swdx_rm_spill_buffer_addr_r(),
@@ -673,7 +674,7 @@ static void gr_gp10b_update_ctxsw_preemption_mode(struct gk20a *g,
true); true);
gr_gk20a_ctx_patch_write(g, ch_ctx, gr_gk20a_ctx_patch_write(g, ch_ctx,
gr_gpc0_swdx_rm_spill_buffer_size_r(), gr_gpc0_swdx_rm_spill_buffer_size_r(),
gr_gpc0_swdx_rm_spill_buffer_size_256b_f(addr), gr_gpc0_swdx_rm_spill_buffer_size_256b_f(size),
true); true);
cbes_reserve = gr_gpcs_swdx_beta_cb_ctrl_cbes_reserve_gfxp_v(); cbes_reserve = gr_gpcs_swdx_beta_cb_ctrl_cbes_reserve_gfxp_v();