diff --git a/Makefile.umbrella.tmk b/Makefile.umbrella.tmk index 1d7e3590c..6d0551857 100644 --- a/Makefile.umbrella.tmk +++ b/Makefile.umbrella.tmk @@ -29,6 +29,7 @@ NV_REPOSITORY_COMPONENTS += userspace/units/posix/fault-injection NV_REPOSITORY_COMPONENTS += userspace/units/pramin NV_REPOSITORY_COMPONENTS += userspace/units/mm/nvgpu_allocator NV_REPOSITORY_COMPONENTS += userspace/units/fifo/runlist +NV_REPOSITORY_COMPONENTS += userspace/units/fuse endif # Local Variables: diff --git a/drivers/gpu/nvgpu/libnvgpu-drv.export b/drivers/gpu/nvgpu/libnvgpu-drv.export index 96c57796e..f79a8f028 100644 --- a/drivers/gpu/nvgpu/libnvgpu-drv.export +++ b/drivers/gpu/nvgpu/libnvgpu-drv.export @@ -40,7 +40,9 @@ nvgpu_free nvgpu_free_enabled_flags nvgpu_free_fixed nvgpu_init_enabled_flags +nvgpu_init_hal nvgpu_init_pramin +nvgpu_is_enabled nvgpu_kmem_cache_alloc nvgpu_kmem_cache_create nvgpu_kmem_cache_destroy diff --git a/drivers/gpu/nvgpu/os/posix/fuse.c b/drivers/gpu/nvgpu/os/posix/fuse.c index 09ec36dca..54a600186 100644 --- a/drivers/gpu/nvgpu/os/posix/fuse.c +++ b/drivers/gpu/nvgpu/os/posix/fuse.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved. + * Copyright (c) 2017-2018, NVIDIA CORPORATION. All rights reserved. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), @@ -45,7 +45,9 @@ void nvgpu_tegra_fuse_write_opt_gpu_tpc1_disable(struct gk20a *g, u32 val) int nvgpu_tegra_fuse_read_gcplex_config_fuse(struct gk20a *g, u32 *val) { - return -ENODEV; + *val = 0; + + return 0; } int nvgpu_tegra_fuse_read_reserved_calib(struct gk20a *g, u32 *val) diff --git a/userspace/Makefile.sources b/userspace/Makefile.sources index f3371a968..585366fc0 100644 --- a/userspace/Makefile.sources +++ b/userspace/Makefile.sources @@ -52,6 +52,7 @@ UNITS := \ $(UNIT_SRC)/posix/mockio \ $(UNIT_SRC)/posix/fault-injection \ $(UNIT_SRC)/pramin \ + $(UNIT_SRC)/fuse \ $(UNIT_SRC)/mm/nvgpu_allocator \ $(UNIT_SRC)/fifo/runlist \ $(UNIT_SRC)/list diff --git a/userspace/units/fuse/Makefile b/userspace/units/fuse/Makefile new file mode 100644 index 000000000..041f1c217 --- /dev/null +++ b/userspace/units/fuse/Makefile @@ -0,0 +1,27 @@ +# Copyright (c) 2018, NVIDIA CORPORATION. All rights reserved. +# +# Permission is hereby granted, free of charge, to any person obtaining a +# copy of this software and associated documentation files (the "Software"), +# to deal in the Software without restriction, including without limitation +# the rights to use, copy, modify, merge, publish, distribute, sublicense, +# and/or sell copies of the Software, and to permit persons to whom the +# Software is furnished to do so, subject to the following conditions: +# +# The above copyright notice and this permission notice shall be included in +# all copies or substantial portions of the Software. +# +# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +# THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER +# LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING +# FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER +# DEALINGS IN THE SOFTWARE. + +.SUFFIXES: + +OBJS = nvgpu-fuse.o \ + nvgpu-fuse-gp10b.o +MODULE = nvgpu-fuse + +include ../Makefile.units diff --git a/userspace/units/fuse/Makefile.interface.tmk b/userspace/units/fuse/Makefile.interface.tmk new file mode 100644 index 000000000..8c4a3a77a --- /dev/null +++ b/userspace/units/fuse/Makefile.interface.tmk @@ -0,0 +1,22 @@ +################################### tell Emacs this is a -*- makefile-gmake -*- +# +# Copyright (c) 2018, NVIDIA CORPORATION. All Rights Reserved. +# +# NVIDIA CORPORATION and its licensors retain all intellectual property +# and proprietary rights in and to this software, related documentation +# and any modifications thereto. Any use, reproduction, disclosure or +# distribution of this software and related documentation without an express +# license agreement from NVIDIA CORPORATION is strictly prohibited. +# +# tmake for SW Mobile component makefile +# +############################################################################### + +NVGPU_UNIT_NAME=nvgpu-fuse +include $(NV_COMPONENT_DIR)/../Makefile.units.common.interface.tmk + +# Local Variables: +# indent-tabs-mode: t +# tab-width: 8 +# End: +# vi: set tabstop=8 noexpandtab: diff --git a/userspace/units/fuse/Makefile.tmk b/userspace/units/fuse/Makefile.tmk new file mode 100644 index 000000000..593c32653 --- /dev/null +++ b/userspace/units/fuse/Makefile.tmk @@ -0,0 +1,25 @@ +################################### tell Emacs this is a -*- makefile-gmake -*- +# +# Copyright (c) 2018 NVIDIA CORPORATION. All Rights Reserved. +# +# NVIDIA CORPORATION and its licensors retain all intellectual property +# and proprietary rights in and to this software, related documentation +# and any modifications thereto. Any use, reproduction, disclosure or +# distribution of this software and related documentation without an express +# license agreement from NVIDIA CORPORATION is strictly prohibited. +# +# tmake for SW Mobile component makefile +# +############################################################################### + +NVGPU_UNIT_NAME=nvgpu-fuse +NVGPU_UNIT_SRCS=nvgpu-fuse.c \ + nvgpu-fuse-gp10b.c + +include $(NV_COMPONENT_DIR)/../Makefile.units.common.tmk + +# Local Variables: +# indent-tabs-mode: t +# tab-width: 8 +# End: +# vi: set tabstop=8 noexpandtab: diff --git a/userspace/units/fuse/nvgpu-fuse-gp10b.c b/userspace/units/fuse/nvgpu-fuse-gp10b.c new file mode 100644 index 000000000..8acdec081 --- /dev/null +++ b/userspace/units/fuse/nvgpu-fuse-gp10b.c @@ -0,0 +1,267 @@ +/* + * Copyright (c) 2018, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#include +#include +#include +#include +#include +#include "common/fuse/fuse_gm20b.h" + +#include "nvgpu-fuse-priv.h" +#include "nvgpu-fuse-gp10b.h" + +#define GP10B_FUSE_REG_BASE 0x00021000U +#define GP10B_FUSE_OPT_SEC_DEBUG_EN (GP10B_FUSE_REG_BASE+0x218U) +#define GP10B_FUSE_OPT_ECC_EN (GP10B_FUSE_REG_BASE+0x228U) +#define GP10B_FUSE_OPT_FEATURE_FUSES_OVERRIDE_DISABLE \ + (GP10B_FUSE_REG_BASE+0x3f0U) +#define GP10B_FUSE_OPT_PRIV_SEC_EN (GP10B_FUSE_REG_BASE+0x434U) + +/* for common init args */ +struct fuse_test_args gp10b_init_args = { + .gpu_arch = 0x13, + .gpu_impl = 0xb, + .fuse_base_addr = GP10B_FUSE_REG_BASE, + .sec_fuse_addr = GP10B_FUSE_OPT_PRIV_SEC_EN, +}; + +/* + * Verify fuse API check_priv_security() when security fuse is enabled. + * Tests with secure debug enabled and disabled. + */ +int test_fuse_gp10b_check_sec(struct unit_module *m, + struct gk20a *g, void *__args) +{ + int ret = UNIT_SUCCESS; + int result; + u32 i; + + nvgpu_posix_io_writel_reg_space(g, GP10B_FUSE_OPT_PRIV_SEC_EN, 0x1); + + gcplex_config = GCPLEX_CONFIG_WPR_ENABLED_MASK & + ~GCPLEX_CONFIG_VPR_AUTO_FETCH_DISABLE_MASK; + + for (i = 0; i < 2; i++) { + nvgpu_posix_io_writel_reg_space(g, GP10B_FUSE_OPT_SEC_DEBUG_EN, + i); + + result = g->ops.fuse.check_priv_security(g); + if (result != 0) { + unit_err(m, "%s: fuse_check_priv_security returned " + "error %d\n", __func__, result); + ret = UNIT_FAIL; + } + + if (!nvgpu_is_enabled(g, NVGPU_SEC_PRIVSECURITY)) { + unit_err(m, "%s: NVGPU_SEC_PRIVSECURITY disabled\n", + __func__); + ret = UNIT_FAIL; + } + + if (!nvgpu_is_enabled(g, NVGPU_SEC_SECUREGPCCS)) { + unit_err(m, "%s: NVGPU_SEC_SECUREGPCCS disabled\n", + __func__); + ret = UNIT_FAIL; + } + } + + return ret; +} + +/* + * Verify fuse API check_priv_security() handles an error from reading gcplex + */ +int test_fuse_gp10b_check_gcplex_fail(struct unit_module *m, + struct gk20a *g, void *__args) +{ + int ret = UNIT_SUCCESS; + int result; + + g->ops.fuse.read_gcplex_config_fuse = read_gcplex_config_fuse_fail; + result = g->ops.fuse.check_priv_security(g); + if (result == 0) { + unit_err(m, "%s: fuse_check_priv_security should have returned " + " error\n", __func__); + ret = UNIT_FAIL; + } + + g->ops.fuse.read_gcplex_config_fuse = read_gcplex_config_fuse_pass; + + return ret; +} + +/* + * Verify fuse API check_priv_security() handles invalid gcplex configurations + * of WPR and VPR bits. + */ +int test_fuse_gp10b_check_sec_invalid_gcplex(struct unit_module *m, + struct gk20a *g, void *__args) +{ + int ret = UNIT_SUCCESS; + int result; + u32 gcplex_values[] = { + 0, + ~GCPLEX_CONFIG_WPR_ENABLED_MASK & + GCPLEX_CONFIG_VPR_AUTO_FETCH_DISABLE_MASK, + GCPLEX_CONFIG_WPR_ENABLED_MASK | + GCPLEX_CONFIG_VPR_AUTO_FETCH_DISABLE_MASK, + }; + int gcplex_entries = sizeof(gcplex_values)/sizeof(gcplex_values[0]); + int i; + + nvgpu_posix_io_writel_reg_space(g, GP10B_FUSE_OPT_PRIV_SEC_EN, 0x1); + + for (i = 0; i < gcplex_entries; i++) { + gcplex_config = gcplex_values[i]; + result = g->ops.fuse.check_priv_security(g); + if (result == 0) { + unit_err(m, "%s: fuse_check_priv_security should have returned " + "error, i = %d, gcplex_config = %x\n", + __func__, i, gcplex_config); + ret = UNIT_FAIL; + } + } + + return ret; +} + + +/* + * Verify fuse API check_priv_security() when security fuse is enabled. + */ +int test_fuse_gp10b_check_non_sec(struct unit_module *m, + struct gk20a *g, void *__args) +{ + int ret = UNIT_SUCCESS; + int result; + + nvgpu_posix_io_writel_reg_space(g, GP10B_FUSE_OPT_PRIV_SEC_EN, 0x0); + + result = g->ops.fuse.check_priv_security(g); + if (result != 0) { + unit_err(m, "%s: fuse_check_priv_security returned " + "error %d\n", __func__, result); + ret = UNIT_FAIL; + } + + if (nvgpu_is_enabled(g, NVGPU_SEC_PRIVSECURITY)) { + unit_err(m, "%s: NVGPU_SEC_PRIVSECURITY enabled\n", __func__); + ret = UNIT_FAIL; + } + + if (nvgpu_is_enabled(g, NVGPU_SEC_SECUREGPCCS)) { + unit_err(m, "%s: NVGPU_SEC_SECUREGPCCS enabled\n", __func__); + ret = UNIT_FAIL; + } + + return ret; +} + +/* Verify fuse reports ECC enable correctly */ +int test_fuse_gp10b_ecc(struct unit_module *m, + struct gk20a *g, void *__args) +{ + bool result; + int ret = UNIT_SUCCESS; + + nvgpu_posix_io_writel_reg_space(g, GP10B_FUSE_OPT_ECC_EN, 0x0); + + result = g->ops.fuse.is_opt_ecc_enable(g); + + if (result) { + unit_err(m, "%s: ECC should be disabled\n", __func__); + ret = UNIT_FAIL; + } + + nvgpu_posix_io_writel_reg_space(g, GP10B_FUSE_OPT_ECC_EN, 0x1); + + result = g->ops.fuse.is_opt_ecc_enable(g); + + if (!result) { + unit_err(m, "%s: ECC should be enabled\n", __func__); + ret = UNIT_FAIL; + } + + return ret; +} + +/* Verify fuse reports feature override correctly */ +int test_fuse_gp10b_feature_override_disable(struct unit_module *m, + struct gk20a *g, void *__args) +{ + bool result; + int ret = UNIT_SUCCESS; + + nvgpu_posix_io_writel_reg_space(g, + GP10B_FUSE_OPT_FEATURE_FUSES_OVERRIDE_DISABLE, 0x0); + + result = g->ops.fuse.is_opt_feature_override_disable(g); + + if (result) { + unit_err(m, "%s: Feature Override should be false\n", __func__); + ret = UNIT_FAIL; + } + + nvgpu_posix_io_writel_reg_space(g, + GP10B_FUSE_OPT_FEATURE_FUSES_OVERRIDE_DISABLE, 0x0); + + result = g->ops.fuse.is_opt_feature_override_disable(g); + + if (result) { + unit_err(m, "%s: Feature Override should be true\n", __func__); + ret = UNIT_FAIL; + } + + return ret; +} + +/* Verify when FMODEL is enabled, fuse module reports non-secure */ +int test_fuse_gp10b_check_fmodel(struct unit_module *m, + struct gk20a *g, void *__args) +{ + int ret = UNIT_SUCCESS; + int result; + + __nvgpu_set_enabled(g, NVGPU_IS_FMODEL, true); + + result = g->ops.fuse.check_priv_security(g); + if (result != 0) { + unit_err(m, "%s: fuse_check_priv_security returned " + "error %d\n", __func__, result); + ret = UNIT_FAIL; + } + + if (nvgpu_is_enabled(g, NVGPU_SEC_PRIVSECURITY)) { + unit_err(m, "%s: NVGPU_SEC_PRIVSECURITY enabled\n", __func__); + ret = UNIT_FAIL; + } + + if (nvgpu_is_enabled(g, NVGPU_SEC_SECUREGPCCS)) { + unit_err(m, "%s: NVGPU_SEC_SECUREGPCCS enabled\n", __func__); + ret = UNIT_FAIL; + } + + __nvgpu_set_enabled(g, NVGPU_IS_FMODEL, false); + return ret; +} + diff --git a/userspace/units/fuse/nvgpu-fuse-gp10b.h b/userspace/units/fuse/nvgpu-fuse-gp10b.h new file mode 100644 index 000000000..781e5823b --- /dev/null +++ b/userspace/units/fuse/nvgpu-fuse-gp10b.h @@ -0,0 +1,43 @@ +/* + * Copyright (c) 2018, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef __UNIT_NVGPU_FUSE_GP10B_H__ +#define __UNIT_NVGPU_FUSE_GP10B_H__ + +extern struct fuse_test_args gp10b_init_args; + +int test_fuse_gp10b_check_sec(struct unit_module *m, + struct gk20a *g, void *__args); +int test_fuse_gp10b_check_gcplex_fail(struct unit_module *m, + struct gk20a *g, void *__args); +int test_fuse_gp10b_check_sec_invalid_gcplex(struct unit_module *m, + struct gk20a *g, void *__args); +int test_fuse_gp10b_check_non_sec(struct unit_module *m, + struct gk20a *g, void *__args); +int test_fuse_gp10b_ecc(struct unit_module *m, + struct gk20a *g, void *__args); +int test_fuse_gp10b_feature_override_disable(struct unit_module *m, + struct gk20a *g, void *__args); +int test_fuse_gp10b_check_fmodel(struct unit_module *m, + struct gk20a *g, void *__args); + +#endif /* __UNIT_NVGPU_FUSE_GP10B_H__ */ diff --git a/userspace/units/fuse/nvgpu-fuse-priv.h b/userspace/units/fuse/nvgpu-fuse-priv.h new file mode 100644 index 000000000..b441659d0 --- /dev/null +++ b/userspace/units/fuse/nvgpu-fuse-priv.h @@ -0,0 +1,37 @@ +/* + * Copyright (c) 2018, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef __UNIT_NVGPU_FUSE_PRIV_H__ +#define __UNIT_NVGPU_FUSE_PRIV_H__ + +extern u32 gcplex_config; +int read_gcplex_config_fuse_pass(struct gk20a *g, u32 *val); +int read_gcplex_config_fuse_fail(struct gk20a *g, u32 *val); + +struct fuse_test_args { + u32 gpu_arch; + u32 gpu_impl; + u32 fuse_base_addr; + u32 sec_fuse_addr; +}; + +#endif /* __UNIT_NVGPU_FUSE_PRIV_H__ */ diff --git a/userspace/units/fuse/nvgpu-fuse.c b/userspace/units/fuse/nvgpu-fuse.c new file mode 100644 index 000000000..0f3cc11b3 --- /dev/null +++ b/userspace/units/fuse/nvgpu-fuse.c @@ -0,0 +1,159 @@ +/* + * Copyright (c) 2018, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#include +#include +#include + +#include +#include +#include + +#include "nvgpu-fuse-priv.h" +#include "nvgpu-fuse-gp10b.h" + +/* + * Mock I/O + */ + +/* + * Write callback. Forward the write access to the mock IO framework. + */ +static void writel_access_reg_fn(struct gk20a *g, + struct nvgpu_reg_access *access) +{ + nvgpu_posix_io_writel_reg_space(g, access->addr, access->value); +} + +/* + * Read callback. Get the register value from the mock IO framework. + */ +static void readl_access_reg_fn(struct gk20a *g, + struct nvgpu_reg_access *access) +{ + access->value = nvgpu_posix_io_readl_reg_space(g, access->addr); +} + +static struct nvgpu_posix_io_callbacks test_reg_callbacks = { + /* Write APIs all can use the same accessor. */ + .writel = writel_access_reg_fn, + .writel_check = writel_access_reg_fn, + .bar1_writel = writel_access_reg_fn, + .usermode_writel = writel_access_reg_fn, + + /* Likewise for the read APIs. */ + .__readl = readl_access_reg_fn, + .readl = readl_access_reg_fn, + .bar1_readl = readl_access_reg_fn, +}; + +/* + * Overrides for the fuse functionality + */ + +u32 gcplex_config; + +/* Return pass and value for reading gcplex */ +int read_gcplex_config_fuse_pass(struct gk20a *g, u32 *val) +{ + *val = gcplex_config; + return 0; +} + +/* Return fail for reading gcplex */ +int read_gcplex_config_fuse_fail(struct gk20a *g, u32 *val) +{ + return -ENODEV; +} + +/* + * Initialization for this unit test. + * Setup g struct + * Setup fuse ops + * Setup mock I/O + */ +static int test_fuse_device_common_init(struct unit_module *m, + struct gk20a *g, void *__args) +{ + int ret = UNIT_SUCCESS; + int result; + struct fuse_test_args *args = (struct fuse_test_args *)__args; + + /* Create fuse register space */ + nvgpu_posix_io_init_reg_space(g); + if (nvgpu_posix_io_add_reg_space(g, args->fuse_base_addr, 0xfff) != 0) { + unit_err(m, "%s: failed to create register space\n", + __func__); + return UNIT_FAIL; + } + + (void)nvgpu_posix_register_io(g, &test_reg_callbacks); + + g->params.gpu_arch = args->gpu_arch << NVGPU_GPU_ARCHITECTURE_SHIFT; + g->params.gpu_impl = args->gpu_impl; + + nvgpu_posix_io_writel_reg_space(g, args->sec_fuse_addr, 0x0); + + result = nvgpu_init_hal(g); + if (result != 0) { + unit_err(m, "%s: nvgpu_init_hal returned error %d\n", + __func__, result); + ret = UNIT_FAIL; + } + + g->ops.fuse.read_gcplex_config_fuse = read_gcplex_config_fuse_pass; + + return ret; +} + +static int test_fuse_device_common_cleanup(struct unit_module *m, + struct gk20a *g, void *__args) +{ + struct fuse_test_args *args = (struct fuse_test_args *)__args; + + nvgpu_posix_io_delete_reg_space(g, args->fuse_base_addr); + + return 0; +} + +struct unit_module_test fuse_tests[] = { + UNIT_TEST(fuse_gp10b_init, test_fuse_device_common_init, + &gp10b_init_args), + UNIT_TEST(fuse_gp10b_check_sec, test_fuse_gp10b_check_sec, NULL), + UNIT_TEST(fuse_gp10b_check_gcplex_fail, + test_fuse_gp10b_check_gcplex_fail, + NULL), + UNIT_TEST(fuse_gp10b_check_sec_invalid_gcplex, + test_fuse_gp10b_check_sec_invalid_gcplex, + NULL), + UNIT_TEST(fuse_gp10b_check_non_sec, + test_fuse_gp10b_check_non_sec, + NULL), + UNIT_TEST(fuse_gp10b_ecc, test_fuse_gp10b_ecc, NULL), + UNIT_TEST(fuse_gp10b_feature_override_disable, + test_fuse_gp10b_feature_override_disable, NULL), + UNIT_TEST(fuse_gp10b_check_fmodel, test_fuse_gp10b_check_fmodel, NULL), + UNIT_TEST(fuse_gp10b_cleanup, test_fuse_device_common_cleanup, + &gp10b_init_args), +}; + +UNIT_MODULE(fuse, fuse_tests, UNIT_PRIO_NVGPU_TEST);