nv-tegra-mirror/linux-nvgpu
1
0
Fork 0
mirror of git://nv-tegra.nvidia.com/linux-nvgpu.git synced 2025-12-24 10:34:43 +03:00
Code Issues Packages Projects Releases Wiki Activity

gpu: nvgpu: Moving chip-agnostic SDL APIs

Browse Source 
This patch restructures the position of chip-agnostic SDL related APIs
from HALs. Specifically, it moves nvgpu_*_report_ecc_error APIs from
LTC, PMU, HUBMMU, and GR units of gv11b.

Jira NVGPU-2722

Change-Id: I19424ee71083dd3cbc0d0021e5e3721e436082a6
Signed-off-by: Rajesh Devaraj <rdevaraj@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2034849
Reviewed-by: Raghuram Kothakota <rkothakota@nvidia.com>
Reviewed-by: svc-misra-checker <svc-misra-checker@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Ankur Kishore <ankkishore@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
This commit is contained in:
Rajesh Devaraj
2019-03-07 16:59:21 +05:30
committed by mobile promotions
parent 8ac8b27ba4
commit cf7d338c8a
6 changed files with 157 additions and 143 deletions
Download Patch File Download Diff File Expand all files Collapse all files

91
drivers/gpu/nvgpu/common/ecc.c
View File

@@ -1,5 +1,5 @@
/*
* Copyright (c) 2018, NVIDIA CORPORATION. All rights reserved.
* Copyright (c) 2018-2019, NVIDIA CORPORATION. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
@@ -22,6 +22,7 @@
#include <nvgpu/gk20a.h>
#include <nvgpu/gr/config.h>
#include <nvgpu/nvgpu_err.h>
static void nvgpu_ecc_stat_add(struct gk20a *g, struct nvgpu_ecc_stat *stat)
{
@@ -373,3 +374,91 @@ void nvgpu_ecc_remove_support(struct gk20a *g)
nvgpu_ecc_sysfs_remove(g);
nvgpu_ecc_free(g);
}
void nvgpu_hubmmu_report_ecc_error(struct gk20a *g, u32 inst,
u32 err_type, u64 err_addr, u64 err_cnt)
{
int ret = 0;
if (g->ops.fb.err_ops.report_ecc_parity_err == NULL) {
return;
}
ret = g->ops.fb.err_ops.report_ecc_parity_err(g,
NVGPU_ERR_MODULE_HUBMMU, inst, err_type, err_addr,
err_cnt);
if (ret != 0) {
nvgpu_err(g, "Failed to report HUBMMU error: inst=%u, "
"err_type=%u, err_addr=%llu, err_cnt=%llu",
inst, err_type, err_addr, err_cnt);
}
}
void nvgpu_ltc_report_ecc_error(struct gk20a *g, u32 ltc, u32 slice,
u32 err_type, u64 err_addr, u64 err_cnt)
{
int ret = 0;
u32 inst = 0U;
if (g->ops.ltc.err_ops.report_ecc_parity_err == NULL) {
return;
}
if (slice < 256U) {
inst = (ltc << 8U) | slice;
} else {
nvgpu_err(g, "Invalid slice id=%u", slice);
return;
}
ret = g->ops.ltc.err_ops.report_ecc_parity_err(g,
NVGPU_ERR_MODULE_LTC, inst, err_type, err_addr,
err_cnt);
if (ret != 0) {
nvgpu_err(g, "Failed to report LTC error: inst=%u, \
err_type=%u, err_addr=%llu, err_cnt=%llu",
inst, err_type, err_addr, err_cnt);
}
}
void nvgpu_pmu_report_ecc_error(struct gk20a *g, u32 inst,
u32 err_type, u64 err_addr, u64 err_cnt)
{
int ret = 0;
if (g->ops.pmu.err_ops.report_ecc_parity_err == NULL) {
return;
}
ret = g->ops.pmu.err_ops.report_ecc_parity_err(g,
NVGPU_ERR_MODULE_PWR, inst, err_type, err_addr,
err_cnt);
if (ret != 0) {
nvgpu_err(g, "Failed to report PMU error: inst=%u, \
err_type=%u, err_addr=%llu, err_cnt=%llu",
inst, err_type, err_addr, err_cnt);
}
}
void nvgpu_gr_report_ecc_error(struct gk20a *g, u32 hw_module,
u32 gpc, u32 tpc, u32 err_type,
u64 err_addr, u64 err_cnt)
{
int ret = 0;
u32 inst = 0U;
if (g->ops.gr.err_ops.report_ecc_parity_err == NULL) {
return;
}
if (tpc < 256U) {
inst = (gpc << 8) | tpc;
} else {
nvgpu_err(g, "Invalid tpc id=%u", tpc);
return;
}
ret = g->ops.gr.err_ops.report_ecc_parity_err(g,
hw_module, inst, err_type,
err_addr, err_cnt);
if (ret != 0) {
nvgpu_err(g, "Failed to report GR error: hw_module=%u, \
inst=%u, err_type=%u, err_addr=%llu, \
err_cnt=%llu", hw_module, inst, err_type,
err_addr, err_cnt);
}
}