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gpu: nvgpu: read fuse reg using physical gpc-id

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Fuse registers should be queried with physical gpc-id and not the
logical ones. For tu104 and before chips physical gpc-ids are same as
logical for non-floorswept config but for newer chips it may differ.
Also, logical to physical mapping is not present for a floorswept gpc so
query gpc_tpc mask only upto actual gpcs that are present.

Jira NVGPU-6080

Change-Id: I84c4a3c1f256fdd1927f4365af26e9892fe91beb
Signed-off-by: shashank singh <shashsingh@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2417721
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
This commit is contained in:
shashank singh
2020-09-22 11:40:38 +05:30
committed by Alex Waterman
parent 78fb67bb0b
commit d003fa57df
4 changed files with 67 additions and 40 deletions
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8
drivers/gpu/nvgpu/os/linux/sysfs.c
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@@ -28,6 +28,8 @@
#include <nvgpu/gr/gr_falcon.h>
#include <nvgpu/gr/gr.h>
#include <nvgpu/gr/gr_utils.h>
#include <nvgpu/gr/gr_instances.h>
#include <nvgpu/grmgr.h>
#include <nvgpu/power_features/cg.h>
#include <nvgpu/power_features/pg.h>
#include <nvgpu/pmu/pmu_perfmon.h>
@@ -947,6 +949,8 @@ static ssize_t tpc_fs_mask_read(struct device *dev,
u32 gpc_index;
u32 tpc_fs_mask = 0;
int err = 0;
u32 cur_gr_instance = nvgpu_gr_get_cur_instance_id(g);
u32 gpc_phys_id;
err = gk20a_busy(g);
if (err)
@@ -955,9 +959,11 @@ static ssize_t tpc_fs_mask_read(struct device *dev,
for (gpc_index = 0;
gpc_index < nvgpu_gr_config_get_gpc_count(gr_config);
gpc_index++) {
gpc_phys_id = nvgpu_grmgr_get_gr_gpc_phys_id(g,
cur_gr_instance, gpc_index);
if (g->ops.gr.config.get_gpc_tpc_mask)
tpc_fs_mask |=
g->ops.gr.config.get_gpc_tpc_mask(g, gr_config, gpc_index) <<
g->ops.gr.config.get_gpc_tpc_mask(g, gr_config, gpc_phys_id) <<
(nvgpu_gr_config_get_max_tpc_per_gpc_count(gr_config) * gpc_index);
}