diff --git a/drivers/gpu/nvgpu/common/fifo/engines.c b/drivers/gpu/nvgpu/common/fifo/engines.c
index 1df5b3ee1..fed9543b4 100644
--- a/drivers/gpu/nvgpu/common/fifo/engines.c
+++ b/drivers/gpu/nvgpu/common/fifo/engines.c
@@ -43,6 +43,9 @@
 #include <nvgpu/fifo.h>
 #include <nvgpu/static_analysis.h>
 #include <nvgpu/gops_mc.h>
+#include <nvgpu/swprofile.h>
+
+#include <nvgpu/fifo/swprofile.h>
 
 #define FECS_METHOD_WFI_RESTORE	0x80000U
 
@@ -551,6 +554,7 @@ void nvgpu_engine_reset(struct gk20a *g, u32 engine_id)
 {
 	enum nvgpu_fifo_engine engine_enum = NVGPU_ENGINE_INVAL;
 	struct nvgpu_engine_info *engine_info;
+	struct nvgpu_swprofiler *prof = &g->fifo.eng_reset_profiler;
 
 	nvgpu_log_fn(g, " ");
 
@@ -558,6 +562,8 @@ void nvgpu_engine_reset(struct gk20a *g, u32 engine_id)
 		return;
 	}
 
+	nvgpu_swprofile_begin_sample(prof);
+
 	engine_info = nvgpu_engine_get_active_eng_info(g, engine_id);
 
 	if (engine_info != NULL) {
@@ -568,12 +574,15 @@ void nvgpu_engine_reset(struct gk20a *g, u32 engine_id)
 		nvgpu_err(g, "unsupported engine_id %d", engine_id);
 	}
 
+	nvgpu_swprofile_snapshot(prof, PROF_ENG_RESET_PREAMBLE);
+
 	if (engine_enum == NVGPU_ENGINE_GR) {
 #ifdef CONFIG_NVGPU_POWER_PG
 		if (nvgpu_pg_elpg_disable(g) != 0 ) {
 			nvgpu_err(g, "failed to set disable elpg");
 		}
 #endif
+		nvgpu_swprofile_snapshot(prof, PROF_ENG_RESET_ELPG_DISABLE);
 
 #ifdef CONFIG_NVGPU_FECS_TRACE
 		/*
@@ -586,6 +595,9 @@ void nvgpu_engine_reset(struct gk20a *g, u32 engine_id)
 			}
 		}
 #endif
+
+		nvgpu_swprofile_snapshot(prof, PROF_ENG_RESET_FECS_TRACE_RESET);
+
 		if (!nvgpu_platform_is_simulation(g)) {
 			int err = 0;
 
@@ -596,6 +608,8 @@ void nvgpu_engine_reset(struct gk20a *g, u32 engine_id)
 				nvgpu_err(g, "failed to halt gr pipe");
 			}
 
+			nvgpu_swprofile_snapshot(prof, PROF_ENG_RESET_HALT_PIPELINE);
+
 			/*
 			 * resetting engine using mc_enable_r() is not
 			 * enough, we do full init sequence
@@ -606,6 +620,7 @@ void nvgpu_engine_reset(struct gk20a *g, u32 engine_id)
 			if (err != 0) {
 				nvgpu_err(g, "failed to reset gr engine");
 			}
+			nvgpu_swprofile_snapshot(prof, PROF_ENG_RESET_GR_RESET);
 		} else {
 			nvgpu_log(g, gpu_dbg_info,
 				"HALT gr pipe not supported and "
@@ -619,6 +634,8 @@ void nvgpu_engine_reset(struct gk20a *g, u32 engine_id)
 #endif
 	}
 
+	nvgpu_swprofile_snapshot(prof, PROF_ENG_RESET_ELPG_REENABLE);
+
 	if ((engine_enum == NVGPU_ENGINE_GRCE) ||
 		(engine_enum == NVGPU_ENGINE_ASYNC_CE)) {
 #if defined(CONFIG_NVGPU_NON_FUSA) && defined(CONFIG_NVGPU_NEXT)
diff --git a/drivers/gpu/nvgpu/common/fifo/fifo.c b/drivers/gpu/nvgpu/common/fifo/fifo.c
index c44925925..9fd1da579 100644
--- a/drivers/gpu/nvgpu/common/fifo/fifo.c
+++ b/drivers/gpu/nvgpu/common/fifo/fifo.c
@@ -46,6 +46,10 @@ static const char *nvgpu_fifo_recovery_profile_events[] = {
 	NVGPU_FIFO_RECOVERY_PROFILE_EVENTS,
 };
 
+static const char *nvgpu_fifo_engine_reset_events[] = {
+	NVGPU_FIFO_ENGINE_RESET_EVENTS,
+};
+
 void nvgpu_fifo_cleanup_sw_common(struct gk20a *g)
 {
 	struct nvgpu_fifo *f = &g->fifo;
@@ -107,6 +111,9 @@ int nvgpu_fifo_setup_sw_common(struct gk20a *g)
 				 nvgpu_fifo_kickoff_profile_events);
 	nvgpu_swprofile_initialize(g, &f->recovery_profiler,
 				 nvgpu_fifo_recovery_profile_events);
+	nvgpu_swprofile_initialize(g, &f->eng_reset_profiler,
+				 nvgpu_fifo_engine_reset_events);
+
 
 	err = nvgpu_channel_setup_sw(g);
 	if (err != 0) {
diff --git a/drivers/gpu/nvgpu/include/nvgpu/fifo.h b/drivers/gpu/nvgpu/include/nvgpu/fifo.h
index fe6dfd7df..90bc5da94 100644
--- a/drivers/gpu/nvgpu/include/nvgpu/fifo.h
+++ b/drivers/gpu/nvgpu/include/nvgpu/fifo.h
@@ -290,6 +290,7 @@ struct nvgpu_fifo {
 
 	struct nvgpu_swprofiler kickoff_profiler;
 	struct nvgpu_swprofiler recovery_profiler;
+	struct nvgpu_swprofiler eng_reset_profiler;
 
 #ifdef CONFIG_NVGPU_USERD
 	struct nvgpu_mutex userd_mutex;
diff --git a/drivers/gpu/nvgpu/include/nvgpu/fifo/swprofile.h b/drivers/gpu/nvgpu/include/nvgpu/fifo/swprofile.h
index e057d6146..4aff5f000 100644
--- a/drivers/gpu/nvgpu/include/nvgpu/fifo/swprofile.h
+++ b/drivers/gpu/nvgpu/include/nvgpu/fifo/swprofile.h
@@ -73,5 +73,24 @@
 #define PROF_RECOVERY_ENABLE_RL			7U
 #define PROF_RECOVERY_DONE			8U
 
+/*
+ * Engine reset profiling - essentially part of the recovery sequence. This
+ * is a big portion of the time spent in recovery.
+ */
+#define NVGPU_FIFO_ENGINE_RESET_EVENTS		\
+	"preamble",				\
+	"elpg_disable",				\
+	"fecs_trace_reset",			\
+	"halt_pipeline",			\
+	"gr_reset",				\
+	"elpg_reenable",			\
+	NULL
+
+#define PROF_ENG_RESET_PREAMBLE			0U
+#define PROF_ENG_RESET_ELPG_DISABLE		1U
+#define PROF_ENG_RESET_FECS_TRACE_RESET		2U
+#define PROF_ENG_RESET_HALT_PIPELINE		3U
+#define PROF_ENG_RESET_GR_RESET			4U
+#define PROF_ENG_RESET_ELPG_REENABLE		5U
 
 #endif
diff --git a/drivers/gpu/nvgpu/os/linux/debug_fifo.c b/drivers/gpu/nvgpu/os/linux/debug_fifo.c
index d4b89a3f6..03f9a141d 100644
--- a/drivers/gpu/nvgpu/os/linux/debug_fifo.c
+++ b/drivers/gpu/nvgpu/os/linux/debug_fifo.c
@@ -150,6 +150,10 @@ void gk20a_fifo_debugfs_init(struct gk20a *g)
 	debugfs_create_file("sched", 0600, fifo_root, g,
 		&gk20a_fifo_sched_debugfs_fops);
 
-	nvgpu_debugfs_swprofile_init(g, fifo_root, &g->fifo.kickoff_profiler, "kickoff_profiler");
-	nvgpu_debugfs_swprofile_init(g, fifo_root, &g->fifo.recovery_profiler, "recovery_profiler");
+	nvgpu_debugfs_swprofile_init(g, fifo_root, &g->fifo.kickoff_profiler,
+				     "kickoff_profiler");
+	nvgpu_debugfs_swprofile_init(g, fifo_root, &g->fifo.recovery_profiler,
+				     "recovery_profiler");
+	nvgpu_debugfs_swprofile_init(g, fifo_root, &g->fifo.eng_reset_profiler,
+				     "eng_reset_profiler");
 }