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gpu: nvgpu: remove gfxp_wfi_timeout_count/unit fields from gr.ctx_vars struct

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gfxp_wfi_timeout_count/unit fields were stored in gr_gk20a.ctx_vars
struct so that any user could configure them through sysfs nodes

But the sysfs nodes are legacy and not being actively used by anyone.
Hence delete the sysfs nodes to configure these fields.

Since the gfxp timeout unit/count can now be statically programmed,
make following changes
- remove g->ops.gr.init_gfxp_wfi_timeout_count() hal
- remove g->ops.gr.get_max_gfxp_wfi_timeout_count() hal
- update g->ops.gr.init.preemption_state() hals to configure the values
  using macros instead of caller passing the values
- update g->ops.gr.init.gfxp_wfi_timeout() hals to configure the values
  using macros instead of caller passing the values

Finally, we don't need to store gfxp_wfi_timeout_count/unit fields
anymore, hence delete them from gr_gk20a.ctx_vars

Jira NVGPU-3112

Change-Id: Idbe5ab3053228dd177aca253545aac36d38ca8ad
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2100219
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Vinod Gopalakrishnakurup <vinodg@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
This commit is contained in:
Deepak Nibade
2019-04-17 17:08:20 +05:30
committed by mobile promotions
parent 77140c1a84
commit d0907087c1
18 changed files with 18 additions and 203 deletions
Download Patch File Download Diff File Expand all files Collapse all files

7
drivers/gpu/nvgpu/common/gr/gr.c
View File

@@ -230,8 +230,7 @@ static int gr_init_setup_hw(struct gk20a *g)
}
if (g->ops.gr.init.preemption_state != NULL) {
err = g->ops.gr.init.preemption_state(g, gr->gfxp_wfi_timeout_count,
gr->gfxp_wfi_timeout_unit_usec);
err = g->ops.gr.init.preemption_state(g);
if (err != 0) {
goto out;
}
@@ -442,10 +441,6 @@ static int gr_init_setup_sw(struct gk20a *g)
goto clean_up;
}
if (g->ops.gr.init_gfxp_wfi_timeout_count != NULL) {
g->ops.gr.init_gfxp_wfi_timeout_count(g);
}
err = nvgpu_mutex_init(&gr->ctx_mutex);
if (err != 0) {
nvgpu_err(g, "Error in gr.ctx_mutex initialization");

7
drivers/gpu/nvgpu/common/gr/obj_ctx.c
View File

@@ -263,8 +263,7 @@ void nvgpu_gr_obj_ctx_update_ctxsw_preemption_mode(struct gk20a *g,
g->ops.gr.init.commit_cbes_reserve(g, gr_ctx, true);
if (g->ops.gr.init.gfxp_wfi_timeout != NULL) {
g->ops.gr.init.gfxp_wfi_timeout(g, gr_ctx,
g->gr->gfxp_wfi_timeout_count, true);
g->ops.gr.init.gfxp_wfi_timeout(g, gr_ctx, true);
}
if (g->ops.gr.init.commit_gfxp_rtv_cb != NULL) {
@@ -445,9 +444,7 @@ int nvgpu_gr_obj_ctx_alloc_golden_ctx_image(struct gk20a *g,
}
if (g->ops.gr.init.preemption_state != NULL) {
err = g->ops.gr.init.preemption_state(g,
g->gr->gfxp_wfi_timeout_count,
g->gr->gfxp_wfi_timeout_unit_usec);
err = g->ops.gr.init.preemption_state(g);
if (err != 0) {
goto clean_up;
}

4
drivers/gpu/nvgpu/common/vgpu/gp10b/vgpu_hal_gp10b.c
View File

@@ -176,10 +176,6 @@ static const struct gpu_ops vgpu_gp10b_ops = {
.pre_process_sm_exception = NULL,
.set_bes_crop_debug3 = NULL,
.set_bes_crop_debug4 = NULL,
.init_gfxp_wfi_timeout_count =
gr_gp10b_init_gfxp_wfi_timeout_count,
.get_max_gfxp_wfi_timeout_count =
gr_gp10b_get_max_gfxp_wfi_timeout_count,
.decode_priv_addr = gr_gk20a_decode_priv_addr,
.create_priv_addr_table = gr_gk20a_create_priv_addr_table,
.split_fbpa_broadcast_addr = gr_gk20a_split_fbpa_broadcast_addr,

4
drivers/gpu/nvgpu/common/vgpu/gv11b/vgpu_hal_gv11b.c
View File

@@ -210,10 +210,6 @@ static const struct gpu_ops vgpu_gv11b_ops = {
.handle_tpc_sm_ecc_exception =
gr_gv11b_handle_tpc_sm_ecc_exception,
.decode_egpc_addr = gv11b_gr_decode_egpc_addr,
.init_gfxp_wfi_timeout_count =
gr_gv11b_init_gfxp_wfi_timeout_count,
.get_max_gfxp_wfi_timeout_count =
gr_gv11b_get_max_gfxp_wfi_timeout_count,
.decode_priv_addr = gr_gv11b_decode_priv_addr,
.create_priv_addr_table = gr_gv11b_create_priv_addr_table,
.split_fbpa_broadcast_addr = gr_gk20a_split_fbpa_broadcast_addr,

3
drivers/gpu/nvgpu/gk20a/gr_gk20a.h
View File

@@ -101,9 +101,6 @@ struct nvgpu_gr {
u32 num_fbps;
u32 max_fbps_count;
u32 gfxp_wfi_timeout_count;
bool gfxp_wfi_timeout_unit_usec;
struct nvgpu_gr_global_ctx_buffer_desc *global_ctx_buffer;
struct nvgpu_gr_obj_ctx_golden_image *golden_image;

17
drivers/gpu/nvgpu/gp10b/gr_gp10b.c
View File

@@ -55,10 +55,6 @@
#include <nvgpu/hw/gp10b/hw_gr_gp10b.h>
#include <nvgpu/hw/gp10b/hw_fifo_gp10b.h>
#define GFXP_WFI_TIMEOUT_COUNT_DEFAULT 100000U
static void gr_gp10b_sm_lrf_ecc_overcount_war(bool single_err,
u32 sed_status,
u32 ded_status,
@@ -1187,16 +1183,3 @@ int gr_gp10b_get_preemption_mode_flags(struct gk20a *g,
return 0;
}
void gr_gp10b_init_gfxp_wfi_timeout_count(struct gk20a *g)
{
struct nvgpu_gr *gr = g->gr;
gr->gfxp_wfi_timeout_count = GFXP_WFI_TIMEOUT_COUNT_DEFAULT;
}
unsigned long gr_gp10b_get_max_gfxp_wfi_timeout_count(struct gk20a *g)
{
/* 100msec @ 1GHZ */
return (100UL * 1000UL * 1000UL);
}

2
drivers/gpu/nvgpu/gp10b/gr_gp10b.h
View File

@@ -86,8 +86,6 @@ int gr_gp10b_get_preemption_mode_flags(struct gk20a *g,
struct nvgpu_preemption_modes_rec *preemption_modes_rec);
int gp10b_gr_fuse_override(struct gk20a *g);
int gr_gp10b_init_preemption_state(struct gk20a *g);
void gr_gp10b_init_gfxp_wfi_timeout_count(struct gk20a *g);
unsigned long gr_gp10b_get_max_gfxp_wfi_timeout_count(struct gk20a *g);
bool gr_gp10b_suspend_context(struct channel_gk20a *ch,
bool *cilp_preempt_pending);
#endif /* NVGPU_GR_GP10B_H */

20
drivers/gpu/nvgpu/gv11b/gr_gv11b.c
View File

@@ -65,8 +65,6 @@
#include <nvgpu/hw/gv11b/hw_proj_gv11b.h>
#include <nvgpu/hw/gv11b/hw_perf_gv11b.h>
#define GFXP_WFI_TIMEOUT_COUNT_IN_USEC_DEFAULT 100U
u32 gr_gv11b_ctxsw_checksum_mismatch_mailbox_val(void)
{
return gr_fecs_ctxsw_mailbox_value_ctxsw_checksum_mismatch_v();
@@ -2802,24 +2800,6 @@ u32 gv11b_gr_get_egpc_base(struct gk20a *g)
return EGPC_PRI_BASE;
}
void gr_gv11b_init_gfxp_wfi_timeout_count(struct gk20a *g)
{
struct nvgpu_gr *gr = g->gr;
gr->gfxp_wfi_timeout_unit_usec = true;
gr->gfxp_wfi_timeout_count = GFXP_WFI_TIMEOUT_COUNT_IN_USEC_DEFAULT;
}
unsigned long gr_gv11b_get_max_gfxp_wfi_timeout_count(struct gk20a *g)
{
if (g->gr->gfxp_wfi_timeout_unit_usec) {
/* 100 msec in usec count */
return (100UL * 1000UL);
} else {
/* 100 msec for 1GHz clock */
return (100UL * 1000UL * 1000UL);
}
}
int gr_gv11b_handle_ssync_hww(struct gk20a *g, u32 *ssync_esr)
{
u32 ssync = gk20a_readl(g, gr_ssync_hww_esr_r());

2
drivers/gpu/nvgpu/gv11b/gr_gv11b.h
View File

@@ -151,8 +151,6 @@ void gv11b_gr_egpc_etpc_priv_addr_table(struct gk20a *g, u32 addr,
u32 *priv_addr_table, u32 *t);
u32 gv11b_gr_get_egpc_base(struct gk20a *g);
int gr_gv11b_init_preemption_state(struct gk20a *g);
void gr_gv11b_init_gfxp_wfi_timeout_count(struct gk20a *g);
unsigned long gr_gv11b_get_max_gfxp_wfi_timeout_count(struct gk20a *g);
int gr_gv11b_handle_ssync_hww(struct gk20a *g, u32 *ssync_esr);
u32 gv11b_gr_sm_offset(struct gk20a *g, u32 sm);

6
drivers/gpu/nvgpu/hal/gr/init/gr_init_gp10b.c
View File

@@ -35,6 +35,8 @@
#include <nvgpu/hw/gp10b/hw_gr_gp10b.h>
#define GFXP_WFI_TIMEOUT_COUNT_DEFAULT 100000U
void gp10b_gr_init_get_access_map(struct gk20a *g,
u32 **whitelist, int *num_entries)
{
@@ -226,10 +228,10 @@ int gp10b_gr_init_fs_state(struct gk20a *g)
return 0;
}
int gp10b_gr_init_preemption_state(struct gk20a *g, u32 gfxp_wfi_timeout_count,
bool gfxp_wfi_timeout_unit_usec)
int gp10b_gr_init_preemption_state(struct gk20a *g)
{
u32 debug_2;
u32 gfxp_wfi_timeout_count = GFXP_WFI_TIMEOUT_COUNT_DEFAULT;
nvgpu_writel(g, gr_fe_gfxp_wfi_timeout_r(),
gr_fe_gfxp_wfi_timeout_count_f(gfxp_wfi_timeout_count));

3
drivers/gpu/nvgpu/hal/gr/init/gr_init_gp10b.h
View File

@@ -36,8 +36,7 @@ int gp10b_gr_init_sm_id_config(struct gk20a *g, u32 *tpc_sm_id,
struct nvgpu_gr_config *gr_config);
int gp10b_gr_init_wait_empty(struct gk20a *g);
int gp10b_gr_init_fs_state(struct gk20a *g);
int gp10b_gr_init_preemption_state(struct gk20a *g, u32 gfxp_wfi_timeout_count,
bool gfxp_wfi_timeout_unit_usec);
int gp10b_gr_init_preemption_state(struct gk20a *g);
u32 gp10b_gr_init_get_attrib_cb_default_size(struct gk20a *g);
u32 gp10b_gr_init_get_alpha_cb_default_size(struct gk20a *g);

18
drivers/gpu/nvgpu/hal/gr/init/gr_init_gv11b.c
View File

@@ -46,6 +46,8 @@
*/
#define GR_TPCS_INFO_FOR_MAPREGISTER 6U
#define GFXP_WFI_TIMEOUT_COUNT_IN_USEC_DEFAULT 100U
static int gr_gv11b_ecc_scrub_is_done(struct gk20a *g,
struct nvgpu_gr_config *gr_config,
u32 scrub_reg, u32 scrub_mask, u32 scrub_done)
@@ -615,24 +617,16 @@ int gv11b_gr_init_fs_state(struct gk20a *g)
return err;
}
int gv11b_gr_init_preemption_state(struct gk20a *g, u32 gfxp_wfi_timeout_count,
bool gfxp_wfi_timeout_unit_usec)
int gv11b_gr_init_preemption_state(struct gk20a *g)
{
u32 debug_2;
u32 unit;
nvgpu_log_fn(g, " ");
if (gfxp_wfi_timeout_unit_usec) {
unit = gr_debug_2_gfxp_wfi_timeout_unit_usec_f();
} else {
unit = gr_debug_2_gfxp_wfi_timeout_unit_sysclk_f();
}
debug_2 = nvgpu_readl(g, gr_debug_2_r());
debug_2 = set_field(debug_2,
gr_debug_2_gfxp_wfi_timeout_unit_m(),
unit);
gr_debug_2_gfxp_wfi_timeout_unit_usec_f());
nvgpu_writel(g, gr_debug_2_r(), debug_2);
return 0;
@@ -885,10 +879,10 @@ void gv11b_gr_init_commit_cbes_reserve(struct gk20a *g,
}
void gv11b_gr_init_commit_gfxp_wfi_timeout(struct gk20a *g,
struct nvgpu_gr_ctx *gr_ctx, u32 timeout, bool patch)
struct nvgpu_gr_ctx *gr_ctx, bool patch)
{
nvgpu_gr_ctx_patch_write(g, gr_ctx, gr_fe_gfxp_wfi_timeout_r(),
timeout, patch);
GFXP_WFI_TIMEOUT_COUNT_IN_USEC_DEFAULT, patch);
}
u32 gv11b_gr_init_get_max_subctx_count(void)

5
drivers/gpu/nvgpu/hal/gr/init/gr_init_gv11b.h
View File

@@ -45,8 +45,7 @@ void gv11b_gr_init_tpc_mask(struct gk20a *g, u32 gpc_index, u32 pes_tpc_mask);
int gv11b_gr_init_rop_mapping(struct gk20a *g,
struct nvgpu_gr_config *gr_config);
int gv11b_gr_init_fs_state(struct gk20a *g);
int gv11b_gr_init_preemption_state(struct gk20a *g, u32 gfxp_wfi_timeout_count,
bool gfxp_wfi_timeout_unit_usec);
int gv11b_gr_init_preemption_state(struct gk20a *g);
void gv11b_gr_init_commit_global_timeslice(struct gk20a *g);
u32 gv11b_gr_init_get_bundle_cb_default_size(struct gk20a *g);
@@ -76,7 +75,7 @@ void gv11b_gr_init_commit_ctxsw_spill(struct gk20a *g,
void gv11b_gr_init_commit_cbes_reserve(struct gk20a *g,
struct nvgpu_gr_ctx *gr_ctx, bool patch);
void gv11b_gr_init_commit_gfxp_wfi_timeout(struct gk20a *g,
struct nvgpu_gr_ctx *gr_ctx, u32 timeout, bool patch);
struct nvgpu_gr_ctx *gr_ctx, bool patch);
u32 gv11b_gr_init_get_max_subctx_count(void);
u32 gv11b_gr_init_get_patch_slots(struct gk20a *g,

4
drivers/gpu/nvgpu/hal/init/hal_gp10b.c
View File

@@ -329,10 +329,6 @@ static const struct gpu_ops gp10b_ops = {
.set_boosted_ctx = gr_gp10b_set_boosted_ctx,
.pre_process_sm_exception = gr_gp10b_pre_process_sm_exception,
.set_bes_crop_debug3 = gr_gp10b_set_bes_crop_debug3,
.init_gfxp_wfi_timeout_count =
gr_gp10b_init_gfxp_wfi_timeout_count,
.get_max_gfxp_wfi_timeout_count =
gr_gp10b_get_max_gfxp_wfi_timeout_count,
.decode_priv_addr = gr_gk20a_decode_priv_addr,
.create_priv_addr_table = gr_gk20a_create_priv_addr_table,
.split_fbpa_broadcast_addr = gr_gk20a_split_fbpa_broadcast_addr,

4
drivers/gpu/nvgpu/hal/init/hal_gv11b.c
View File

@@ -411,10 +411,6 @@ static const struct gpu_ops gv11b_ops = {
.handle_tpc_sm_ecc_exception =
gr_gv11b_handle_tpc_sm_ecc_exception,
.decode_egpc_addr = gv11b_gr_decode_egpc_addr,
.init_gfxp_wfi_timeout_count =
gr_gv11b_init_gfxp_wfi_timeout_count,
.get_max_gfxp_wfi_timeout_count =
gr_gv11b_get_max_gfxp_wfi_timeout_count,
.handle_ssync_hww = gr_gv11b_handle_ssync_hww,
.decode_priv_addr = gr_gv11b_decode_priv_addr,
.create_priv_addr_table = gr_gv11b_create_priv_addr_table,

4
drivers/gpu/nvgpu/hal/init/hal_tu104.c
View File

@@ -459,10 +459,6 @@ static const struct gpu_ops tu104_ops = {
.handle_tpc_sm_ecc_exception =
gr_gv11b_handle_tpc_sm_ecc_exception,
.decode_egpc_addr = gv11b_gr_decode_egpc_addr,
.init_gfxp_wfi_timeout_count =
gr_gv11b_init_gfxp_wfi_timeout_count,
.get_max_gfxp_wfi_timeout_count =
gr_gv11b_get_max_gfxp_wfi_timeout_count,
.handle_ssync_hww = gr_gv11b_handle_ssync_hww,
.decode_priv_addr = gr_gv11b_decode_priv_addr,
.create_priv_addr_table = gr_gv11b_create_priv_addr_table,

10
drivers/gpu/nvgpu/include/nvgpu/gk20a.h
View File

@@ -393,9 +393,6 @@ struct gpu_ops {
void (*resume_single_sm)(struct gk20a *g,
u32 gpc, u32 tpc, u32 sm);
void (*resume_all_sms)(struct gk20a *g);
void (*init_gfxp_wfi_timeout_count)(struct gk20a *g);
unsigned long (*get_max_gfxp_wfi_timeout_count)
(struct gk20a *g);
int (*handle_ssync_hww)(struct gk20a *g, u32 *ssync_esr);
int (*add_ctxsw_reg_pm_fbpa)(struct gk20a *g,
struct ctxsw_buf_offset_map_entry *map,
@@ -720,9 +717,7 @@ struct gpu_ops {
int (*fe_pwr_mode_force_on)(struct gk20a *g,
bool force_on);
void (*override_context_reset)(struct gk20a *g);
int (*preemption_state)(struct gk20a *g,
u32 gfxp_wfi_timeout_count,
bool gfxp_wfi_timeout_unit_usec);
int (*preemption_state)(struct gk20a *g);
void (*fe_go_idle_timeout)(struct gk20a *g,
bool enable);
void (*load_method_init)(struct gk20a *g,
@@ -782,8 +777,7 @@ struct gpu_ops {
void (*commit_cbes_reserve)(struct gk20a *g,
struct nvgpu_gr_ctx *gr_ctx, bool patch);
void (*gfxp_wfi_timeout)(struct gk20a *g,
struct nvgpu_gr_ctx *gr_ctx, u32 timeout,
bool patch);
struct nvgpu_gr_ctx *gr_ctx, bool patch);
u32 (*get_max_subctx_count)(void);
u32 (*get_patch_slots)(struct gk20a *g,
struct nvgpu_gr_config *config);

101
drivers/gpu/nvgpu/os/linux/sysfs.c
View File

@@ -985,103 +985,6 @@ static ssize_t max_timeslice_us_store(struct device *dev,
static DEVICE_ATTR(max_timeslice_us, ROOTRW, max_timeslice_us_read,
max_timeslice_us_store);
static ssize_t gfxp_wfi_timeout_count_store(struct device *dev,
struct device_attribute *attr, const char *buf, size_t count)
{
struct gk20a *g = get_gk20a(dev);
struct nvgpu_gr *gr = g->gr;
unsigned long val = 0;
int err = -1;
if (kstrtoul(buf, 10, &val) < 0)
return -EINVAL;
if (g->ops.gr.get_max_gfxp_wfi_timeout_count) {
if (val >= g->ops.gr.get_max_gfxp_wfi_timeout_count(g))
return -EINVAL;
}
gr->gfxp_wfi_timeout_count = val;
if (g->ops.gr.init.preemption_state && g->power_on) {
err = gk20a_busy(g);
if (err)
return err;
err = nvgpu_pg_elpg_protected_call(g,
g->ops.gr.init.preemption_state(g,
gr->gfxp_wfi_timeout_count,
gr->gfxp_wfi_timeout_unit_usec));
gk20a_idle(g);
if (err)
return err;
}
return count;
}
static ssize_t gfxp_wfi_timeout_unit_store(struct device *dev,
struct device_attribute *attr, const char *buf, size_t count)
{
struct gk20a *g = get_gk20a(dev);
struct nvgpu_gr *gr = g->gr;
int err = -1;
if (count > 0 && buf[0] == 's')
/* sysclk */
gr->gfxp_wfi_timeout_unit_usec = false;
else
/* usec */
gr->gfxp_wfi_timeout_unit_usec = true;
if (g->ops.gr.init.preemption_state && g->power_on) {
err = gk20a_busy(g);
if (err)
return err;
err = nvgpu_pg_elpg_protected_call(g,
g->ops.gr.init.preemption_state(g,
gr->gfxp_wfi_timeout_count,
gr->gfxp_wfi_timeout_unit_usec));
gk20a_idle(g);
if (err)
return err;
}
return count;
}
static ssize_t gfxp_wfi_timeout_count_read(struct device *dev,
struct device_attribute *attr, char *buf)
{
struct gk20a *g = get_gk20a(dev);
struct nvgpu_gr *gr = g->gr;
u32 val = gr->gfxp_wfi_timeout_count;
return snprintf(buf, PAGE_SIZE, "%d\n", val);
}
static ssize_t gfxp_wfi_timeout_unit_read(struct device *dev,
struct device_attribute *attr, char *buf)
{
struct gk20a *g = get_gk20a(dev);
struct nvgpu_gr *gr = g->gr;
if (gr->gfxp_wfi_timeout_unit_usec)
return snprintf(buf, PAGE_SIZE, "usec\n");
else
return snprintf(buf, PAGE_SIZE, "sysclk\n");
}
static DEVICE_ATTR(gfxp_wfi_timeout_count, (S_IRWXU|S_IRGRP|S_IROTH),
gfxp_wfi_timeout_count_read, gfxp_wfi_timeout_count_store);
static DEVICE_ATTR(gfxp_wfi_timeout_unit, (S_IRWXU|S_IRGRP|S_IROTH),
gfxp_wfi_timeout_unit_read, gfxp_wfi_timeout_unit_store);
static ssize_t comptag_mem_deduct_store(struct device *dev,
struct device_attribute *attr,
const char *buf, size_t count)
@@ -1152,8 +1055,6 @@ void nvgpu_remove_sysfs(struct device *dev)
nvgpu_nvhost_remove_symlink(get_gk20a(dev));
#endif
device_remove_file(dev, &dev_attr_gfxp_wfi_timeout_count);
device_remove_file(dev, &dev_attr_gfxp_wfi_timeout_unit);
device_remove_file(dev, &dev_attr_gpu_powered_on);
device_remove_file(dev, &dev_attr_comptag_mem_deduct);
@@ -1205,8 +1106,6 @@ int nvgpu_create_sysfs(struct device *dev)
error |= nvgpu_nvhost_create_symlink(g);
#endif
error |= device_create_file(dev, &dev_attr_gfxp_wfi_timeout_count);
error |= device_create_file(dev, &dev_attr_gfxp_wfi_timeout_unit);
error |= device_create_file(dev, &dev_attr_gpu_powered_on);
error |= device_create_file(dev, &dev_attr_comptag_mem_deduct);