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gpu: nvgpu: Support ELPG feature on nvgpu-next

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Changes:
 -Implemented pg init_send ops for legacy chips.
 -Implemented RPC response handler.
 -Added pg rpc function call macros for nvgpu-next.

NVGPU-5192
NVGPU-5195
NVGPU-5196

Signed-off-by: rmylavarapu <rmylavarapu@nvidia.com>
Change-Id: I4e99d3929d7db796434aaeaa6f5773e9aac9fd32
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2391029
Reviewed-by: automaticguardword <automaticguardword@nvidia.com>
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-cert <svc-mobile-cert@nvidia.com>
Reviewed-by: Mahantesh Kumbar <mkumbar@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
GVS: Gerrit_Virtual_Submit
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
This commit is contained in:
rmylavarapu
2020-07-30 14:13:30 +05:30
committed by Alex Waterman
parent 2dfa05ba50
commit d0c01fc14c
9 changed files with 109 additions and 81 deletions
Download Patch File Download Diff File Expand all files Collapse all files

3
drivers/gpu/nvgpu/include/nvgpu/pmu/pmu_pg.h
View File

@@ -112,6 +112,9 @@ struct nvgpu_pmu_pg {
u8 pg_engine_id);
int (*load_buff)(struct gk20a *g, struct nvgpu_pmu *pmu);
int (*hw_load_zbc)(struct gk20a *g, struct nvgpu_pmu *pmu);
void (*rpc_handler)(struct gk20a *g, struct nvgpu_pmu *pmu,
struct nv_pmu_rpc_header *rpc);
int (*init_send)(struct gk20a *g, struct nvgpu_pmu *pmu, u8 pg_engine_id);
};
/*PG defines used by nvpgu-pmu*/

1
drivers/gpu/nvgpu/include/nvgpu/pmu/pmuif/nvgpu_cmdif.h
View File

@@ -30,6 +30,7 @@
#define PMU_UNIT_REWIND U8(0x00)
#define PMU_UNIT_CMDMGMT U8(0x01)
#define PMU_UNIT_PG U8(0x03)
#define PMU_UNIT_PG_LOADING U8(0x06)
#define PMU_UNIT_INIT U8(0x07)
#define PMU_UNIT_ACR U8(0x0A)
#define PMU_UNIT_PERFMON_T18X U8(0x11)

11
drivers/gpu/nvgpu/include/nvgpu/pmu/pmuif/pg.h
View File

@@ -1,5 +1,5 @@
/*
* Copyright (c) 2017-2019, NVIDIA CORPORATION. All rights reserved.
* Copyright (c) 2017-2020, NVIDIA CORPORATION. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
@@ -35,6 +35,15 @@
#define PMU_PG_ELPG_ENGINE_ID_INVALID_ENGINE (0x00000005U)
#define PMU_PG_ELPG_ENGINE_MAX PMU_PG_ELPG_ENGINE_ID_INVALID_ENGINE
/* RPC function calls supported by PG unit */
#define NV_PMU_RPC_ID_PG_LOADING_PRE_INIT 0x00U
#define NV_PMU_RPC_ID_PG_LOADING_INIT 0x0AU
#define NV_PMU_RPC_ID_PG_LOADING_BUF_LOAD 0x0BU
#define NV_PMU_RPC_ID_PG_ALLOW 0x04U
#define NV_PMU_RPC_ID_PG_DISALLOW 0x05U
#define NV_PMU_RPC_ID_PG_THRESHOLD_UPDATE 0x06U
#define NV_PMU_RPC_ID_PG_SFM_UPDATE 0x08U
/* PG message */
enum {
PMU_PG_ELPG_MSG_INIT_ACK,