From d0ed86ab1e9669af3f69cf0b8ef529b6be3f35f7 Mon Sep 17 00:00:00 2001 From: Prathap Kumar Valsan Date: Fri, 10 Mar 2023 06:27:22 +0000 Subject: [PATCH] gpu: nvgpu: update PT lvl array to six levels Increase the size of page table level array to index six levels. Jira NVGPU-9760 Change-Id: I482639fd028ecd504ee8bc313c39f3bd710e81a9 Signed-off-by: Prathap Kumar Valsan Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2868918 Reviewed-by: svcacv Reviewed-by: svc-mobile-coverity Reviewed-by: svc-mobile-misra Reviewed-by: svc-mobile-cert Reviewed-by: Seema Khowala GVS: Gerrit_Virtual_Submit --- drivers/gpu/nvgpu/common/mm/gmmu/page_table.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/nvgpu/common/mm/gmmu/page_table.c b/drivers/gpu/nvgpu/common/mm/gmmu/page_table.c index e2c24ab7b..bbdbf2637 100644 --- a/drivers/gpu/nvgpu/common/mm/gmmu/page_table.c +++ b/drivers/gpu/nvgpu/common/mm/gmmu/page_table.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2017-2022, NVIDIA CORPORATION. All rights reserved. + * Copyright (c) 2017-2023, NVIDIA CORPORATION. All rights reserved. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), @@ -482,6 +482,7 @@ static int nvgpu_set_pd_level(struct vm_gk20a *vm, " ", /* L=2 */ " ", /* L=3 */ " ", /* L=4 */ + " ",/* L=5 */ }; nvgpu_gmmu_dbg_v(g, attrs,