From d16ddb244fe1a4ce97f31e0631519ba2f2bd508c Mon Sep 17 00:00:00 2001 From: Deepak Nibade Date: Thu, 30 May 2019 13:35:13 +0530 Subject: [PATCH] gpu: nvgpu: remove g->ops.gr.halt_pipe hal Hal API g->ops.gr.halt_pipe() is defined in unsafe unit hal.gr.gr It is called from safe unit, and it calls into API g->ops.gr.falcon.ctrl_ctxsw() which is also safe Hence get rid of unsafe API g->ops.gr.halt_pipe(). Caller now directly calls hal.gr.falcon API to halt pipe Jira NVGPU-3506 Change-Id: I5439cb79431795fc7c22384832cf632d6db03316 Signed-off-by: Deepak Nibade Reviewed-on: https://git-master.nvidia.com/r/2127755 Reviewed-by: svc-mobile-coverity Reviewed-by: svc-mobile-misra GVS: Gerrit_Virtual_Submit Reviewed-by: mobile promotions Tested-by: mobile promotions --- drivers/gpu/nvgpu/common/fifo/engines.c | 10 ++++++++-- drivers/gpu/nvgpu/common/gr/gr.c | 6 ------ drivers/gpu/nvgpu/common/vgpu/gp10b/vgpu_hal_gp10b.c | 1 - drivers/gpu/nvgpu/common/vgpu/gv11b/vgpu_hal_gv11b.c | 1 - drivers/gpu/nvgpu/hal/init/hal_gm20b.c | 1 - drivers/gpu/nvgpu/hal/init/hal_gp10b.c | 1 - drivers/gpu/nvgpu/hal/init/hal_gv11b.c | 1 - drivers/gpu/nvgpu/hal/init/hal_tu104.c | 1 - drivers/gpu/nvgpu/include/nvgpu/gk20a.h | 1 - drivers/gpu/nvgpu/include/nvgpu/gr/gr.h | 1 - 10 files changed, 8 insertions(+), 16 deletions(-) diff --git a/drivers/gpu/nvgpu/common/fifo/engines.c b/drivers/gpu/nvgpu/common/fifo/engines.c index 6fc12bc98..5defafede 100644 --- a/drivers/gpu/nvgpu/common/fifo/engines.c +++ b/drivers/gpu/nvgpu/common/fifo/engines.c @@ -550,17 +550,23 @@ void nvgpu_engine_reset(struct gk20a *g, u32 engine_id) } #endif if (!nvgpu_platform_is_simulation(g)) { + int err = 0; + /*HALT_PIPELINE method, halt GR engine*/ - if (g->ops.gr.halt_pipe(g) != 0) { + err = g->ops.gr.falcon.ctrl_ctxsw(g, + NVGPU_GR_FALCON_METHOD_HALT_PIPELINE, 0U, NULL); + if (err != 0) { nvgpu_err(g, "failed to halt gr pipe"); } + /* * resetting engine using mc_enable_r() is not * enough, we do full init sequence */ nvgpu_log(g, gpu_dbg_info, "resetting gr engine"); - if (g->ops.gr.reset(g) != 0) { + err = g->ops.gr.reset(g); + if (err != 0) { nvgpu_err(g, "failed to reset gr engine"); } } else { diff --git a/drivers/gpu/nvgpu/common/gr/gr.c b/drivers/gpu/nvgpu/common/gr/gr.c index 5f3ec6f7a..41a55b213 100644 --- a/drivers/gpu/nvgpu/common/gr/gr.c +++ b/drivers/gpu/nvgpu/common/gr/gr.c @@ -791,12 +791,6 @@ ctxsw_already_enabled: return err; } -int nvgpu_gr_halt_pipe(struct gk20a *g) -{ - return g->ops.gr.falcon.ctrl_ctxsw(g, - NVGPU_GR_FALCON_METHOD_HALT_PIPELINE, 0U, NULL); -} - void nvgpu_gr_remove_support(struct gk20a *g) { if (g->gr->remove_support != NULL) { diff --git a/drivers/gpu/nvgpu/common/vgpu/gp10b/vgpu_hal_gp10b.c b/drivers/gpu/nvgpu/common/vgpu/gp10b/vgpu_hal_gp10b.c index 6e046d39f..adf072ff2 100644 --- a/drivers/gpu/nvgpu/common/vgpu/gp10b/vgpu_hal_gp10b.c +++ b/drivers/gpu/nvgpu/common/vgpu/gp10b/vgpu_hal_gp10b.c @@ -177,7 +177,6 @@ static const struct gpu_ops vgpu_gp10b_ops = { .set_debug_mode = gm20b_gr_set_debug_mode, .set_mmu_debug_mode = NULL, .reset = NULL, - .halt_pipe = NULL, .disable_ctxsw = nvgpu_gr_disable_ctxsw, .enable_ctxsw = nvgpu_gr_enable_ctxsw, .ctxsw_prog = { diff --git a/drivers/gpu/nvgpu/common/vgpu/gv11b/vgpu_hal_gv11b.c b/drivers/gpu/nvgpu/common/vgpu/gv11b/vgpu_hal_gv11b.c index d98598324..81de854d2 100644 --- a/drivers/gpu/nvgpu/common/vgpu/gv11b/vgpu_hal_gv11b.c +++ b/drivers/gpu/nvgpu/common/vgpu/gv11b/vgpu_hal_gv11b.c @@ -211,7 +211,6 @@ static const struct gpu_ops vgpu_gv11b_ops = { .set_debug_mode = gm20b_gr_set_debug_mode, .set_mmu_debug_mode = NULL, .reset = NULL, - .halt_pipe = NULL, .disable_ctxsw = nvgpu_gr_disable_ctxsw, .enable_ctxsw = nvgpu_gr_enable_ctxsw, .ctxsw_prog = { diff --git a/drivers/gpu/nvgpu/hal/init/hal_gm20b.c b/drivers/gpu/nvgpu/hal/init/hal_gm20b.c index bb2b03cb3..926619f97 100644 --- a/drivers/gpu/nvgpu/hal/init/hal_gm20b.c +++ b/drivers/gpu/nvgpu/hal/init/hal_gm20b.c @@ -189,7 +189,6 @@ static const struct gpu_ops gm20b_ops = { .set_debug_mode = gm20b_gr_set_debug_mode, .reset = nvgpu_gr_reset, .esr_bpt_pending_events = gm20b_gr_esr_bpt_pending_events, - .halt_pipe = nvgpu_gr_halt_pipe, .disable_ctxsw = nvgpu_gr_disable_ctxsw, .enable_ctxsw = nvgpu_gr_enable_ctxsw, .ctxsw_prog = { diff --git a/drivers/gpu/nvgpu/hal/init/hal_gp10b.c b/drivers/gpu/nvgpu/hal/init/hal_gp10b.c index aa70eab0f..a0812d193 100644 --- a/drivers/gpu/nvgpu/hal/init/hal_gp10b.c +++ b/drivers/gpu/nvgpu/hal/init/hal_gp10b.c @@ -222,7 +222,6 @@ static const struct gpu_ops gp10b_ops = { .set_debug_mode = gm20b_gr_set_debug_mode, .reset = nvgpu_gr_reset, .esr_bpt_pending_events = gm20b_gr_esr_bpt_pending_events, - .halt_pipe = nvgpu_gr_halt_pipe, .disable_ctxsw = nvgpu_gr_disable_ctxsw, .enable_ctxsw = nvgpu_gr_enable_ctxsw, .ecc = { diff --git a/drivers/gpu/nvgpu/hal/init/hal_gv11b.c b/drivers/gpu/nvgpu/hal/init/hal_gv11b.c index 568fdbb95..d5e8b513e 100644 --- a/drivers/gpu/nvgpu/hal/init/hal_gv11b.c +++ b/drivers/gpu/nvgpu/hal/init/hal_gv11b.c @@ -276,7 +276,6 @@ static const struct gpu_ops gv11b_ops = { .set_mmu_debug_mode = gm20b_gr_set_mmu_debug_mode, .reset = nvgpu_gr_reset, .esr_bpt_pending_events = gv11b_gr_esr_bpt_pending_events, - .halt_pipe = nvgpu_gr_halt_pipe, .disable_ctxsw = nvgpu_gr_disable_ctxsw, .enable_ctxsw = nvgpu_gr_enable_ctxsw, .ecc = { diff --git a/drivers/gpu/nvgpu/hal/init/hal_tu104.c b/drivers/gpu/nvgpu/hal/init/hal_tu104.c index 340faf62f..5414e412b 100644 --- a/drivers/gpu/nvgpu/hal/init/hal_tu104.c +++ b/drivers/gpu/nvgpu/hal/init/hal_tu104.c @@ -323,7 +323,6 @@ static const struct gpu_ops tu104_ops = { .set_debug_mode = gm20b_gr_set_debug_mode, .reset = nvgpu_gr_reset, .esr_bpt_pending_events = gv11b_gr_esr_bpt_pending_events, - .halt_pipe = nvgpu_gr_halt_pipe, .disable_ctxsw = nvgpu_gr_disable_ctxsw, .enable_ctxsw = nvgpu_gr_enable_ctxsw, .ecc = { diff --git a/drivers/gpu/nvgpu/include/nvgpu/gk20a.h b/drivers/gpu/nvgpu/include/nvgpu/gk20a.h index 7ac9a067e..cc2869c23 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/gk20a.h +++ b/drivers/gpu/nvgpu/include/nvgpu/gk20a.h @@ -387,7 +387,6 @@ struct gpu_ops { int (*reset)(struct gk20a *g); bool (*esr_bpt_pending_events)(u32 global_esr, enum nvgpu_event_id_type bpt_event); - int (*halt_pipe)(struct gk20a *g); int (*disable_ctxsw)(struct gk20a *g); int (*enable_ctxsw)(struct gk20a *g); struct { diff --git a/drivers/gpu/nvgpu/include/nvgpu/gr/gr.h b/drivers/gpu/nvgpu/include/nvgpu/gr/gr.h index 012b8ca1d..b6e7f5f7e 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/gr/gr.h +++ b/drivers/gpu/nvgpu/include/nvgpu/gr/gr.h @@ -44,7 +44,6 @@ int nvgpu_gr_alloc(struct gk20a *g); void nvgpu_gr_free(struct gk20a *g); int nvgpu_gr_disable_ctxsw(struct gk20a *g); int nvgpu_gr_enable_ctxsw(struct gk20a *g); -int nvgpu_gr_halt_pipe(struct gk20a *g); void nvgpu_gr_remove_support(struct gk20a *g); void nvgpu_gr_sw_ready(struct gk20a *g, bool enable); #endif /* NVGPU_GR_H */