From d17b2b9622960056bb56964ba02ccdfb708592f9 Mon Sep 17 00:00:00 2001 From: Seshendra Gadagottu Date: Fri, 7 Jun 2019 12:34:31 -0700 Subject: [PATCH] gpu: nvgpu: fix CERT INT30-C in hal.gr.falcon Fixed CERT C error with following lines by using nvgpu_safe_add_u32: tag++; --> tag = nvgpu_safe_add_u32(tag, 1U); Fixed CERT C error with following lines by nvgpu_gr_checksum_u32: checksum += ucode_u32_data[i]; --> checksum = nvgpu_gr_checksum_u32(checksum, ucode_u32_data[i]); JIRA NVGPU-3622 Change-Id: Id8808365990033e3527605b989b63a4f6d2826f9 Signed-off-by: Seshendra Gadagottu Reviewed-on: https://git-master.nvidia.com/r/2132548 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: svc-mobile-coverity Reviewed-by: svc-mobile-misra GVS: Gerrit_Virtual_Submit Reviewed-by: Vinod Gopalakrishnakurup Reviewed-by: mobile promotions Tested-by: mobile promotions --- .../gpu/nvgpu/hal/gr/falcon/gr_falcon_gm20b.c | 17 +++++++++-------- 1 file changed, 9 insertions(+), 8 deletions(-) diff --git a/drivers/gpu/nvgpu/hal/gr/falcon/gr_falcon_gm20b.c b/drivers/gpu/nvgpu/hal/gr/falcon/gr_falcon_gm20b.c index 97fc32ab8..92af09e53 100644 --- a/drivers/gpu/nvgpu/hal/gr/falcon/gr_falcon_gm20b.c +++ b/drivers/gpu/nvgpu/hal/gr/falcon/gr_falcon_gm20b.c @@ -27,6 +27,7 @@ #include #include #include +#include #include #include "gr_falcon_gm20b.h" @@ -59,7 +60,7 @@ void gm20b_gr_falcon_load_gpccs_dmem(struct gk20a *g, for (i = 0; i < ucode_u32_size; i++) { nvgpu_writel(g, gr_gpccs_dmemd_r(0), ucode_u32_data[i]); - checksum += ucode_u32_data[i]; + checksum = nvgpu_gr_checksum_u32(checksum, ucode_u32_data[i]); } nvgpu_log_info(g, "gpccs dmem checksum: 0x%x", checksum); } @@ -77,7 +78,7 @@ void gm20b_gr_falcon_load_fecs_dmem(struct gk20a *g, for (i = 0; i < ucode_u32_size; i++) { nvgpu_writel(g, gr_fecs_dmemd_r(0), ucode_u32_data[i]); - checksum += ucode_u32_data[i]; + checksum = nvgpu_gr_checksum_u32(checksum, ucode_u32_data[i]); } nvgpu_log_info(g, "fecs dmem checksum: 0x%x", checksum); } @@ -103,12 +104,12 @@ void gm20b_gr_falcon_load_gpccs_imem(struct gk20a *g, for (i = 0; i < ucode_u32_size; i++) { if ((i != 0U) && ((i % (256U/sizeof(u32))) == 0U)) { - tag++; + tag = nvgpu_safe_add_u32(tag, 1U); nvgpu_writel(g, gr_gpccs_imemt_r(0), gr_gpccs_imemt_tag_f(tag)); } nvgpu_writel(g, gr_gpccs_imemd_r(0), ucode_u32_data[i]); - checksum += ucode_u32_data[i]; + checksum = nvgpu_gr_checksum_u32(checksum, ucode_u32_data[i]); } pad_start = nvgpu_safe_mult_u32(i, 4U); @@ -118,7 +119,7 @@ void gm20b_gr_falcon_load_gpccs_imem(struct gk20a *g, (i < nvgpu_safe_mult_u32(gpccs_imem_size, 256U)) && (i < pad_end); i += 4U) { if ((i != 0U) && ((i % 256U) == 0U)) { - tag++; + tag = nvgpu_safe_add_u32(tag, 1U); nvgpu_writel(g, gr_gpccs_imemt_r(0), gr_gpccs_imemt_tag_f(tag)); } @@ -149,12 +150,12 @@ void gm20b_gr_falcon_load_fecs_imem(struct gk20a *g, for (i = 0; i < ucode_u32_size; i++) { if ((i != 0U) && ((i % (256U/sizeof(u32))) == 0U)) { - tag++; + tag = nvgpu_safe_add_u32(tag, 1U); nvgpu_writel(g, gr_fecs_imemt_r(0), gr_fecs_imemt_tag_f(tag)); } nvgpu_writel(g, gr_fecs_imemd_r(0), ucode_u32_data[i]); - checksum += ucode_u32_data[i]; + checksum = nvgpu_gr_checksum_u32(checksum, ucode_u32_data[i]); } pad_start = nvgpu_safe_mult_u32(i, 4U); @@ -164,7 +165,7 @@ void gm20b_gr_falcon_load_fecs_imem(struct gk20a *g, (i < nvgpu_safe_mult_u32(fecs_imem_size, 256U)) && i < pad_end; i += 4U) { if ((i != 0U) && ((i % 256U) == 0U)) { - tag++; + tag = nvgpu_safe_add_u32(tag, 1U); nvgpu_writel(g, gr_fecs_imemt_r(0), gr_fecs_imemt_tag_f(tag)); }