diff --git a/drivers/gpu/nvgpu/libnvgpu-drv_safe.export b/drivers/gpu/nvgpu/libnvgpu-drv_safe.export index ebf18ad97..4f0c80f97 100644 --- a/drivers/gpu/nvgpu/libnvgpu-drv_safe.export +++ b/drivers/gpu/nvgpu/libnvgpu-drv_safe.export @@ -88,6 +88,7 @@ gv11b_blcg_hshub_gating_prod_size gv11b_blcg_hshub_get_gating_prod gv11b_netlist_is_firmware_defined nvgpu_acr_init +nvgpu_acr_is_lsf_lazy_bootstrap nvgpu_alloc nvgpu_alloc_base nvgpu_alloc_common_init diff --git a/userspace/Makefile.tmk b/userspace/Makefile.tmk index 7945ebacc..f47239762 100644 --- a/userspace/Makefile.tmk +++ b/userspace/Makefile.tmk @@ -64,7 +64,11 @@ NV_TESTLIST_PY=testlist.py NV_REQ_TESTS_JSON=required_tests.json NV_NETD_IMG=NETD_img.bin NV_FECS_IMG=fecs.bin +NV_FECS_SIG_IMG=fecs_sig.bin NV_GPCCS_IMG=gpccs.bin +NV_GPCCS_SIG_IMG=gpccs_sig.bin +NV_ACR_UCODE_IMG=acr_ucode.bin +NV_PMU_BL_IMG=pmu_bl.bin NV_COMPONENT_SYSTEMIMAGE_DIR := $(NV_SYSTEMIMAGE_TEST_EXECUTABLE_DIR)/nvgpu_unit NV_UNIT_REQ_FIRMWARE_DIR := $(NV_COMPONENT_SYSTEMIMAGE_DIR)/firmware systemimage:: $(NV_COMPONENT_SYSTEMIMAGE_DIR) $(NV_COMPONENT_SYSTEMIMAGE_DIR)/$(NV_UNIT_SH) \ @@ -73,7 +77,11 @@ systemimage:: $(NV_COMPONENT_SYSTEMIMAGE_DIR) $(NV_COMPONENT_SYSTEMIMAGE_DIR)/$( $(NV_COMPONENT_SYSTEMIMAGE_DIR)/$(NV_REQ_TESTS_JSON) \ $(NV_UNIT_REQ_FIRMWARE_DIR) $(NV_UNIT_REQ_FIRMWARE_DIR)/$(NV_NETD_IMG) \ $(NV_UNIT_REQ_FIRMWARE_DIR)/$(NV_FECS_IMG) \ - $(NV_UNIT_REQ_FIRMWARE_DIR)/$(NV_GPCCS_IMG) + $(NV_UNIT_REQ_FIRMWARE_DIR)/$(NV_FECS_SIG_IMG) \ + $(NV_UNIT_REQ_FIRMWARE_DIR)/$(NV_GPCCS_IMG) \ + $(NV_UNIT_REQ_FIRMWARE_DIR)/$(NV_GPCCS_SIG_IMG) \ + $(NV_UNIT_REQ_FIRMWARE_DIR)/$(NV_ACR_UCODE_IMG) \ + $(NV_UNIT_REQ_FIRMWARE_DIR)/$(NV_PMU_BL_IMG) #make the output directory $(NV_COMPONENT_SYSTEMIMAGE_DIR) : $(NV_SYSTEMIMAGE_TEST_EXECUTABLE_DIR) @@ -95,8 +103,16 @@ $(NV_UNIT_REQ_FIRMWARE_DIR)/$(NV_NETD_IMG) : $(NV_COMPONENT_DIR)/firmware/$(NV_N $(CP) $< $@ $(NV_UNIT_REQ_FIRMWARE_DIR)/$(NV_FECS_IMG) : $(NV_COMPONENT_DIR)/firmware/$(NV_FECS_IMG) $(NV_UNIT_REQ_FIRMWARE_DIR) $(CP) $< $@ +$(NV_UNIT_REQ_FIRMWARE_DIR)/$(NV_FECS_SIG_IMG) : $(NV_COMPONENT_DIR)/firmware/$(NV_FECS_SIG_IMG) $(NV_UNIT_REQ_FIRMWARE_DIR) + $(CP) $< $@ $(NV_UNIT_REQ_FIRMWARE_DIR)/$(NV_GPCCS_IMG) : $(NV_COMPONENT_DIR)/firmware/$(NV_GPCCS_IMG) $(NV_UNIT_REQ_FIRMWARE_DIR) $(CP) $< $@ +$(NV_UNIT_REQ_FIRMWARE_DIR)/$(NV_GPCCS_SIG_IMG) : $(NV_COMPONENT_DIR)/firmware/$(NV_GPCCS_SIG_IMG) $(NV_UNIT_REQ_FIRMWARE_DIR) + $(CP) $< $@ +$(NV_UNIT_REQ_FIRMWARE_DIR)/$(NV_ACR_UCODE_IMG) : $(NV_COMPONENT_DIR)/firmware/$(NV_ACR_UCODE_IMG) $(NV_UNIT_REQ_FIRMWARE_DIR) + $(CP) $< $@ +$(NV_UNIT_REQ_FIRMWARE_DIR)/$(NV_PMU_BL_IMG) : $(NV_COMPONENT_DIR)/firmware/$(NV_PMU_BL_IMG) $(NV_UNIT_REQ_FIRMWARE_DIR) + $(CP) $< $@ include $(NV_BUILD_NVTEST_EXECUTABLE) diff --git a/userspace/firmware/acr_ucode.bin b/userspace/firmware/acr_ucode.bin new file mode 100644 index 000000000..ffbdb1ce1 Binary files /dev/null and b/userspace/firmware/acr_ucode.bin differ diff --git a/userspace/firmware/fecs_sig.bin b/userspace/firmware/fecs_sig.bin new file mode 100644 index 000000000..5762fdd10 Binary files /dev/null and b/userspace/firmware/fecs_sig.bin differ diff --git a/userspace/firmware/gpccs_sig.bin b/userspace/firmware/gpccs_sig.bin new file mode 100644 index 000000000..5762fdd10 Binary files /dev/null and b/userspace/firmware/gpccs_sig.bin differ diff --git a/userspace/firmware/pmu_bl.bin b/userspace/firmware/pmu_bl.bin new file mode 100644 index 000000000..269b1d247 Binary files /dev/null and b/userspace/firmware/pmu_bl.bin differ diff --git a/userspace/required_tests.json b/userspace/required_tests.json index 1fba39103..9462da639 100644 --- a/userspace/required_tests.json +++ b/userspace/required_tests.json @@ -1698,6 +1698,17 @@ "test_level": 0, "unit": "nvgpu-acr" }, + { + "test": "acr_prepare_ucode_blob", + "test_level": 0, + "unit": "nvgpu-acr" + }, + { + "test": "acr_is_lsf_lazy_bootstrap", + "test_level": 0, + "unit": "nvgpu-acr" + }, + { "test": "acr_free_falcon_test_env", "test_level": 0, diff --git a/userspace/units/acr/Makefile b/userspace/units/acr/Makefile index d97ee5ba7..538a54b2b 100644 --- a/userspace/units/acr/Makefile +++ b/userspace/units/acr/Makefile @@ -23,11 +23,16 @@ OBJS = nvgpu-acr.o MODULE = nvgpu-acr -LIB_PATHS += -lfalcon_utf +LIB_PATHS += -lfalcon_utf \ + -lnvgpu-gr include ../Makefile.units -lib$(MODULE).so: falcon_utf +lib$(MODULE).so: falcon_utf \ + nvgpu-gr falcon_utf: $(MAKE) -C ../falcon + +nvgpu-gr: + $(MAKE) -C ../gr diff --git a/userspace/units/acr/Makefile.tmk b/userspace/units/acr/Makefile.tmk index a41a659fd..82bc494b0 100644 --- a/userspace/units/acr/Makefile.tmk +++ b/userspace/units/acr/Makefile.tmk @@ -29,6 +29,7 @@ NVGPU_UNIT_SRCS=nvgpu-acr.c NVGPU_UNIT_INTERFACE_DIRS := \ $(NV_COMPONENT_DIR)/../falcon \ + $(NV_COMPONENT_DIR)/../gr \ $(NV_SOURCE)/kernel/nvgpu/drivers/gpu/nvgpu include $(NV_COMPONENT_DIR)/../Makefile.units.common.tmk diff --git a/userspace/units/acr/nvgpu-acr.c b/userspace/units/acr/nvgpu-acr.c index cbe55ec21..db22ae310 100644 --- a/userspace/units/acr/nvgpu-acr.c +++ b/userspace/units/acr/nvgpu-acr.c @@ -30,13 +30,24 @@ #include #include #include +#include +#include +#include +#include +#include #include +#include +#include +#include +#include #include "nvgpu-acr.h" #include "../falcon/falcon_utf.h" +#include "../gr/nvgpu-gr-gv11b-regs.h" +#include "../gr/nvgpu-gr-gv11b.h" -struct utf_falcon *pmu_flcn; +struct utf_falcon *pmu_flcn, *gpccs_flcn; #define NV_PMC_BOOT_0_ARCHITECTURE_GV110 (0x00000015 << \ NVGPU_GPU_ARCHITECTURE_SHIFT) @@ -46,19 +57,30 @@ struct utf_falcon *pmu_flcn; NVGPU_GPU_ARCHITECTURE_SHIFT) #define NV_PMC_BOOT_0_IMPLEMENTATION_INVALID 0xD -static struct utf_falcon *pmu_flcn_from_addr(struct gk20a *g, u32 addr) +#define NV_PBB_FBHUB_REGSPACE 0x100B00 + +static struct utf_falcon *get_flcn_from_addr(struct gk20a *g, u32 addr) { struct utf_falcon *flcn = NULL; u32 flcn_base; - if (pmu_flcn == NULL || pmu_flcn->flcn == NULL) { + if (pmu_flcn == NULL || gpccs_flcn == NULL) { + return NULL; + } + if (pmu_flcn->flcn == NULL || gpccs_flcn->flcn == NULL) { return NULL; } flcn_base = pmu_flcn->flcn->flcn_base; if ((addr >= flcn_base) && - (addr < (flcn_base + UTF_FALCON_MAX_REG_OFFSET))) { + (addr < (flcn_base + UTF_FALCON_MAX_REG_OFFSET))) { flcn = pmu_flcn; + } else { + flcn_base = gpccs_flcn->flcn->flcn_base; + if ((addr >= flcn_base) && + (addr < (flcn_base + UTF_FALCON_MAX_REG_OFFSET))) { + flcn = gpccs_flcn; + } } return flcn; @@ -69,7 +91,7 @@ static void writel_access_reg_fn(struct gk20a *g, { struct utf_falcon *flcn = NULL; - flcn = pmu_flcn_from_addr(g, access->addr); + flcn = get_flcn_from_addr(g, access->addr); if (flcn != NULL) { nvgpu_utf_falcon_writel_access_reg_fn(g, flcn, access); } else { @@ -83,7 +105,7 @@ static void readl_access_reg_fn(struct gk20a *g, { struct utf_falcon *flcn = NULL; - flcn = pmu_flcn_from_addr(g, access->addr); + flcn = get_flcn_from_addr(g, access->addr); if (flcn != NULL) { nvgpu_utf_falcon_readl_access_reg_fn(g, flcn, access); } else { @@ -139,18 +161,211 @@ static int init_acr_falcon_test_env(struct unit_module *m, struct gk20a *g) return -ENODEV; } + /* + * Register space: FB_MMU + * + */ + if (nvgpu_posix_io_add_reg_space(g, fb_niso_intr_r(), 0x800) != 0) { + unit_return_fail(m, "nvgpu_posix_io_add_reg_space failed\n"); + } + + /* + * Register space: HW_FLUSH + * + */ + if (nvgpu_posix_io_add_reg_space(g, flush_fb_flush_r(), 0x20) != 0) { + unit_return_fail(m, "nvgpu_posix_io_add_reg_space failed\n"); + } + + if (g->ops.mm.is_bar1_supported(g)) { + unit_return_fail(m, "BAR1 is not supported on Volta+\n"); + } + + /* * Initialize utf & nvgpu falcon * for test usage + * */ pmu_flcn = nvgpu_utf_falcon_init(m, g, FALCON_ID_PMU); if (pmu_flcn == NULL) { return -ENODEV; } + gpccs_flcn = nvgpu_utf_falcon_init(m, g, FALCON_ID_GPCCS); + if (gpccs_flcn == NULL) { + return -ENODEV; + } return 0; } +int test_acr_is_lsf_lazy_bootstrap(struct unit_module *m, + struct gk20a *g, void *args) +{ + bool ret = false; + int err; + /* + * initialize falcon + * + */ + if (init_acr_falcon_test_env(m, g) != 0) { + unit_return_fail(m, "Module init failed\n"); + } + + err = test_gr_setup_gv11b_reg_space(m, g); + if (err != 0) { + goto fail; + } + + nvgpu_set_enabled(g, NVGPU_SEC_SECUREGPCCS, true); + err = nvgpu_gr_alloc(g); + if (err != 0) { + unit_err(m, " Gr allocation failed!\n"); + return -ENOMEM; + } + + /* + * initialize PMU + * + */ + err = g->ops.pmu.pmu_early_init(g); + if (err != 0) { + unit_return_fail(m, "nvgpu_pmu_early_init failed\n"); + } + err = g->ops.acr.acr_init(g); + if (err != 0) { + unit_return_fail(m, "nvgpu_acr_init failed\n"); + } + + err = g->ops.mm.init_mm_support(g); + if (err != 0) { + unit_return_fail(m, "failed to init gk20a mm"); + } + + nvgpu_mutex_acquire(&g->tpc_pg_lock); + + /* + * prepare portion of sw required + * for enable hw + * + */ + err = nvgpu_gr_prepare_sw(g); + if (err != 0) { + nvgpu_mutex_release(&g->tpc_pg_lock); + unit_return_fail(m, "failed to prepare sw"); + } + + err = nvgpu_gr_enable_hw(g); + if (err != 0) { + nvgpu_mutex_release(&g->tpc_pg_lock); + unit_return_fail(m, "failed to enable gr"); + } + + /* + * case 1: pass scenario + */ + ret = nvgpu_acr_is_lsf_lazy_bootstrap(g, g->acr, + FALCON_ID_FECS); + if (ret) { + unit_return_fail(m, "failed to test lazy bootstrap\n"); + } + + g->acr = NULL; + ret = nvgpu_acr_is_lsf_lazy_bootstrap(g, g->acr, + FALCON_ID_FECS); + if (ret != false) { + unit_return_fail(m, "lazy bootstrap failure didn't happen as \ + expected\n"); + } + + nvgpu_mutex_release(&g->tpc_pg_lock); + + return UNIT_SUCCESS; + +fail: + return UNIT_FAIL; +} + +int test_acr_prepare_ucode_blob(struct unit_module *m, + struct gk20a *g, void *args) +{ + int err; + + /* + * initialize falcon + * + */ + if (init_acr_falcon_test_env(m, g) != 0) { + unit_return_fail(m, "Module init failed\n"); + } + + err = test_gr_setup_gv11b_reg_space(m, g); + if (err != 0) { + goto fail; + } + + nvgpu_set_enabled(g, NVGPU_SEC_SECUREGPCCS, true); + + err = nvgpu_gr_alloc(g); + if (err != 0) { + unit_err(m, " Gr allocation failed!\n"); + return -ENOMEM; + } + + /* + * initialize PMU + * + */ + err = g->ops.pmu.pmu_early_init(g); + if (err != 0) { + unit_return_fail(m, "nvgpu_pmu_early_init failed\n"); + } + + err = g->ops.acr.acr_init(g); + if (err != 0) { + unit_return_fail(m, "nvgpu_acr_init failed\n"); + } + + err = g->ops.mm.init_mm_support(g); + if (err != 0) { + unit_return_fail(m, "failed to init gk20a mm"); + } + + nvgpu_mutex_acquire(&g->tpc_pg_lock); + + /* + * prepare portion of sw required + * for enable hw + * + */ + err = nvgpu_gr_prepare_sw(g); + if (err != 0) { + nvgpu_mutex_release(&g->tpc_pg_lock); + unit_return_fail(m, "failed to prepare sw"); + } + + err = nvgpu_gr_enable_hw(g); + if (err != 0) { + nvgpu_mutex_release(&g->tpc_pg_lock); + unit_return_fail(m, "failed to enable gr"); + } + + /* case:pass + * + */ + err = g->acr->prepare_ucode_blob(g); + if (err != 0) { + unit_return_fail(m, "test failed\n"); + } + + nvgpu_mutex_release(&g->tpc_pg_lock); + + return UNIT_SUCCESS; + +fail: + return UNIT_FAIL; +} + int test_acr_init(struct unit_module *m, struct gk20a *g, void *args) { @@ -165,6 +380,11 @@ int test_acr_init(struct unit_module *m, unit_return_fail(m, "Module init failed\n"); } + err = test_gr_setup_gv11b_reg_space(m, g); + if (err != 0) { + goto fail; + } + /* * initialize PMU */ @@ -212,13 +432,16 @@ int test_acr_init(struct unit_module *m, */ g->params.gpu_arch = NV_PMC_BOOT_0_ARCHITECTURE_GV110; g->params.gpu_impl = NV_PMC_BOOT_0_IMPLEMENTATION_B; - + g->acr = NULL; err = nvgpu_acr_init(g); if (err != 0) { unit_return_fail(m, "nvgpu_acr_init() failed\n"); } return UNIT_SUCCESS; + +fail: + return UNIT_FAIL; } int free_falcon_test_env(struct unit_module *m, struct gk20a *g, @@ -246,6 +469,9 @@ int free_falcon_test_env(struct unit_module *m, struct gk20a *g, struct unit_module_test nvgpu_acr_tests[] = { UNIT_TEST(acr_init, test_acr_init, NULL, 0), + UNIT_TEST(acr_prepare_ucode_blob, test_acr_prepare_ucode_blob, NULL, 0), + UNIT_TEST(acr_is_lsf_lazy_bootstrap, + test_acr_is_lsf_lazy_bootstrap, NULL, 0), UNIT_TEST(acr_free_falcon_test_env, free_falcon_test_env, NULL, 0), }; diff --git a/userspace/units/acr/nvgpu-acr.h b/userspace/units/acr/nvgpu-acr.h index 254e15ccd..63458b70b 100644 --- a/userspace/units/acr/nvgpu-acr.h +++ b/userspace/units/acr/nvgpu-acr.h @@ -52,6 +52,57 @@ struct unit_module; */ int test_acr_init(struct unit_module *m, struct gk20a *g, void *args); +/** + * Test specification for: test_acr_prepare_ucode_blob + * + * Description: The test_acr_init shall test the blob creation of + * the ACR unit + * + * Test Type: Feature based + * + * Input: None + * Steps: + * - Initialize the falcon test environment + * - Set the flag NVGPU_SEC_SECUREGPCCS + * - Allocate memory for GR + * - Initialize the PMU + * - Initialize the ACR unit + * - Initialize the MMU + * - Prepare SW and HW for GR + * - Prepare ucode BLOB + * + * Output: Returns PASS if the steps above were executed successfully. FAIL + * otherwise. + */ + +int test_acr_prepare_ucode_blob(struct unit_module *m, struct gk20a *g, + void *__args); +/** + * Test specification for: test_acr_is_lsf_lazy_bootstrap + * + * Description: The test_acr_init shall test the lazy bootstrap of + * the ACR unit + * + * Test Type: Feature based + * + * Input: None + * + * Steps: + * - Initialize the falcon test environment + * - Set the flag NVGPU_SEC_SECUREGPCCS + * - Allocate memory for GR + * - Initialize the PMU + * - Initialize the ACR unit + * - Initialize the MMU + * - Prepare SW and HW for GR + * - lsf lazy bootstrap + * + * Output: Returns PASS if the steps above were executed successfully. FAIL + * otherwise. + */ + +int test_acr_is_lsf_lazy_bootstrap(struct unit_module *m, struct gk20a *g, + void *__args); /** * Test specification for: free_falcon_test_env * diff --git a/userspace/units/gr/libnvgpu-gr.export b/userspace/units/gr/libnvgpu-gr.export index 81d19894c..b8e547181 100644 --- a/userspace/units/gr/libnvgpu-gr.export +++ b/userspace/units/gr/libnvgpu-gr.export @@ -26,4 +26,4 @@ test_gr_init_prepare test_gr_init_support test_gr_suspend test_gr_remove_support - +test_gr_setup_gv11b_reg_space