From 9036cf9d228f33c11517bac0e188bac908665fe3 Mon Sep 17 00:00:00 2001 From: Poojan Shah Date: Mon, 7 Jan 2019 22:10:32 -0800 Subject: [PATCH] vgpu: nvclock: Deprecate Clock Get/Set APIs for KHz ESQC-6156 ESQC-6044 Change-Id: Id59a680c78054cd09e02759574ececa83f7f6b5c Signed-off-by: Poojan Shah Reviewed-on: https://git-master.nvidia.com/r/2001172 Reviewed-by: svcboomerang Tested-by: svcboomerang --- drivers/gpu/nvgpu/include/nvgpu/vgpu/tegra_vgpu.h | 6 +++--- drivers/gpu/nvgpu/os/linux/vgpu/vgpu_linux.c | 4 ++-- drivers/gpu/nvgpu/vgpu/clk_vgpu.c | 11 +++++------ 3 files changed, 10 insertions(+), 11 deletions(-) diff --git a/drivers/gpu/nvgpu/include/nvgpu/vgpu/tegra_vgpu.h b/drivers/gpu/nvgpu/include/nvgpu/vgpu/tegra_vgpu.h index 695972624..f1675da93 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/vgpu/tegra_vgpu.h +++ b/drivers/gpu/nvgpu/include/nvgpu/vgpu/tegra_vgpu.h @@ -1,7 +1,7 @@ /* * Tegra GPU Virtualization Interfaces to Server * - * Copyright (c) 2014-2018, NVIDIA CORPORATION. All rights reserved. + * Copyright (c) 2014-2019, NVIDIA CORPORATION. All rights reserved. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), @@ -452,7 +452,7 @@ struct tegra_vgpu_set_powergate_params { }; struct tegra_vgpu_gpu_clk_rate_params { - u32 rate; /* in kHz */ + u64 rate; /* in Hz */ }; struct tegra_vgpu_set_sm_exception_type_mask_params { @@ -486,7 +486,7 @@ struct tegra_vgpu_constants_params { u32 arch; u32 impl; u32 rev; - u32 max_freq; + u64 max_freq; u32 num_channels; u32 golden_ctx_size; u32 zcull_ctx_size; diff --git a/drivers/gpu/nvgpu/os/linux/vgpu/vgpu_linux.c b/drivers/gpu/nvgpu/os/linux/vgpu/vgpu_linux.c index 4dc9a04bc..334e4b6c4 100644 --- a/drivers/gpu/nvgpu/os/linux/vgpu/vgpu_linux.c +++ b/drivers/gpu/nvgpu/os/linux/vgpu/vgpu_linux.c @@ -215,12 +215,12 @@ static int vgpu_qos_notify(struct notifier_block *nb, container_of(nb, struct gk20a_scale_profile, qos_notify_block); struct gk20a *g = get_gk20a(profile->dev); - u32 max_freq; + u64 max_freq; int err; nvgpu_log_fn(g, " "); - max_freq = (u32)pm_qos_read_max_bound(PM_QOS_GPU_FREQ_BOUNDS); + max_freq = (u64)pm_qos_read_max_bound(PM_QOS_GPU_FREQ_BOUNDS) * 1000UL; err = vgpu_plat_clk_cap_rate(profile->dev, max_freq); if (err) nvgpu_err(g, "%s failed, err=%d", __func__, err); diff --git a/drivers/gpu/nvgpu/vgpu/clk_vgpu.c b/drivers/gpu/nvgpu/vgpu/clk_vgpu.c index 74003316d..92be034b5 100644 --- a/drivers/gpu/nvgpu/vgpu/clk_vgpu.c +++ b/drivers/gpu/nvgpu/vgpu/clk_vgpu.c @@ -46,7 +46,7 @@ static unsigned long vgpu_clk_get_rate(struct gk20a *g, u32 api_domain) nvgpu_err(g, "%s failed - %d", __func__, err); else /* return frequency in Hz */ - ret = p->rate * 1000; + ret = p->rate; break; case CTRL_CLK_DOMAIN_PWRCLK: nvgpu_err(g, "unsupported clock: %u", api_domain); @@ -73,8 +73,7 @@ static int vgpu_clk_set_rate(struct gk20a *g, msg.cmd = TEGRA_VGPU_CMD_SET_GPU_CLK_RATE; msg.handle = vgpu_get_handle(g); - /* server dvfs framework requires frequency in kHz */ - p->rate = (u32)(rate / 1000); + p->rate = rate; err = vgpu_comm_sendrecv(&msg, sizeof(msg), sizeof(msg)); err = err ? err : msg.ret; if (err) @@ -224,7 +223,7 @@ int vgpu_clk_get_freqs(struct gk20a *g, unsigned long **freqs_out, struct tegra_vgpu_get_gpu_freq_table_params *p = &msg.params.get_gpu_freq_table; struct vgpu_priv_data *priv = vgpu_get_priv_data(g); - u32 *freqs; + u64 *freqs; int err = 0; void *handle = NULL; size_t oob_size; @@ -267,7 +266,7 @@ int vgpu_clk_get_freqs(struct gk20a *g, unsigned long **freqs_out, for (i = 0; i < priv->num_freqs; i++) { /* store frequency in Hz */ - priv->freqs[i] = (unsigned long)(freqs[i] * 1000); + priv->freqs[i] = (unsigned long)(freqs[i]); } vgpu_ivc_oob_put_ptr(handle); @@ -293,7 +292,7 @@ int vgpu_clk_cap_rate(struct gk20a *g, unsigned long rate) msg.cmd = TEGRA_VGPU_CMD_CAP_GPU_CLK_RATE; msg.handle = vgpu_get_handle(g); - p->rate = (u32)rate; + p->rate = rate; err = vgpu_comm_sendrecv(&msg, sizeof(msg), sizeof(msg)); err = err ? err : msg.ret; if (err) {