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gpu: nvgpu: compiled out clk_arb unit

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clk_arb is a non safe unit, it should be compiled out of safe build

JIRA NVGPU-3499

Change-Id: I9cce04570e52fe3ec73f3a1d3c2744a9a8940592
Signed-off-by: Sagar Kadamati <skadamati@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2143538
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Shashank Singh <shashsingh@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Ankur Kishore <ankkishore@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
This commit is contained in:
Sagar Kadamati
2019-05-23 15:44:06 +05:30
committed by mobile promotions
parent 92f42b293b
commit d24bff61e6
11 changed files with 45 additions and 6 deletions
Download Patch File Download Diff File Expand all files Collapse all files

2
drivers/gpu/nvgpu/hal/init/hal_gp10b.c
View File

@@ -950,6 +950,7 @@ static const struct gpu_ops gp10b_ops = {
.pmu_ns_bootstrap = gk20a_pmu_ns_bootstrap,
},
#endif
#ifdef CONFIG_NVGPU_CLK_ARB
.clk_arb = {
.check_clk_arb_support = gp10b_check_clk_arb_support,
.get_arbiter_clk_domains = gp10b_get_arbiter_clk_domains,
@@ -960,6 +961,7 @@ static const struct gpu_ops gp10b_ops = {
.clk_arb_run_arbiter_cb = gp10b_clk_arb_run_arbiter_cb,
.clk_arb_cleanup = gp10b_clk_arb_cleanup,
},
#endif
#ifdef CONFIG_NVGPU_DEBUGGER
.regops = {
.exec_regops = exec_regops_gk20a,

4
drivers/gpu/nvgpu/hal/init/hal_gv11b.c
View File

@@ -1117,6 +1117,7 @@ static const struct gpu_ops gv11b_ops = {
.pmu_ns_bootstrap = gv11b_pmu_bootstrap,
#endif
},
#ifdef CONFIG_NVGPU_CLK_ARB
.clk_arb = {
.check_clk_arb_support = gp10b_check_clk_arb_support,
.get_arbiter_clk_domains = gp10b_get_arbiter_clk_domains,
@@ -1127,6 +1128,7 @@ static const struct gpu_ops gv11b_ops = {
.clk_arb_run_arbiter_cb = gp10b_clk_arb_run_arbiter_cb,
.clk_arb_cleanup = gp10b_clk_arb_cleanup,
},
#endif
#ifdef CONFIG_NVGPU_DEBUGGER
.regops = {
.exec_regops = exec_regops_gk20a,
@@ -1345,7 +1347,9 @@ int gv11b_init_hal(struct gk20a *g)
gops->falcon = gv11b_ops.falcon;
gops->priv_ring = gv11b_ops.priv_ring;
gops->fuse = gv11b_ops.fuse;
#ifdef CONFIG_NVGPU_CLK_ARB
gops->clk_arb = gv11b_ops.clk_arb;
#endif
gops->top = gv11b_ops.top;
/* Lone functions */

6
drivers/gpu/nvgpu/hal/init/hal_tu104.c
View File

@@ -1155,6 +1155,7 @@ static const struct gpu_ops tu104_ops = {
.clk_domain_get_f_points = gv100_clk_domain_get_f_points,
.get_maxrate = gv100_clk_maxrate,
},
#ifdef CONFIG_NVGPU_CLK_ARB
.clk_arb = {
.check_clk_arb_support = gv100_check_clk_arb_support,
.get_arbiter_clk_domains = gv100_get_arbiter_clk_domains,
@@ -1168,6 +1169,7 @@ static const struct gpu_ops tu104_ops = {
.stop_clk_arb_threads = gv100_stop_clk_arb_threads,
},
#endif
#endif
#ifdef CONFIG_NVGPU_DEBUGGER
.regops = {
.exec_regops = exec_regops_gk20a,
@@ -1497,7 +1499,9 @@ int tu104_init_hal(struct gk20a *g)
gops->clk.get_crystal_clk_hz = tu104_ops.clk.get_crystal_clk_hz;
gops->clk.measure_freq = tu104_ops.clk.measure_freq;
gops->clk.suspend_clk_support = tu104_ops.clk.suspend_clk_support;
#ifdef CONFIG_NVGPU_CLK_ARB
gops->clk_arb = tu104_ops.clk_arb;
#endif
gops->clk.clk_domain_get_f_points = tu104_ops.clk.clk_domain_get_f_points;
gops->clk = tu104_ops.clk;
@@ -1565,7 +1569,9 @@ int tu104_init_hal(struct gk20a *g)
gops->fb.mem_unlock = NULL;
/* Disable clock support */
#ifdef CONFIG_NVGPU_CLK_ARB
gops->clk_arb.get_arbiter_clk_domains = NULL;
#endif
gops->clk.support_clk_freq_controller = false;
} else