gpu: nvgpu: compiled out clk_arb unit

clk_arb is a non safe unit, it should be compiled out of safe build

JIRA NVGPU-3499

Change-Id: I9cce04570e52fe3ec73f3a1d3c2744a9a8940592
Signed-off-by: Sagar Kadamati <skadamati@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2143538
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Shashank Singh <shashsingh@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Ankur Kishore <ankkishore@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>

drivers/gpu/nvgpu/Makefile

@@ -45,6 +45,7 @@ ccflags-y += -DCONFIG_NVGPU_COMPRESSION
 ccflags-y += -DCONFIG_NVGPU_SIM
 ccflags-y += -DCONFIG_NVGPU_TRACE
 ccflags-y += -DCONFIG_NVGPU_SYSFS
+ccflags-y += -DCONFIG_NVGPU_CLK_ARB
 
 ifeq ($(CONFIG_NVGPU_LOGGING),y)
 ccflags-y += -DCONFIG_NVGPU_LOGGING=1

drivers/gpu/nvgpu/Makefile.shared.configs

@@ -166,5 +166,8 @@ NVGPU_COMMON_CFLAGS             += -DCONFIG_NVGPU_CE
 CONFIG_NVGPU_HAL_NON_FUSA       := 1
 NVGPU_COMMON_CFLAGS             += -DCONFIG_NVGPU_HAL_NON_FUSA
 
+CONFIG_NVGPU_CLK_ARB            := 1
+NVGPU_COMMON_CFLAGS             += -DCONFIG_NVGPU_CLK_ARB
+
 endif
 endif

drivers/gpu/nvgpu/Makefile.sources

@@ -32,7 +32,6 @@ srcs +=	os/posix/nvgpu.c \
 	os/posix/soc.c \
 	os/posix/error_notifier.c \
 	os/posix/fuse.c \
-	os/posix/posix-clk_arb.c \
 	os/posix/posix-channel.c \
 	os/posix/posix-tsg.c \
 	os/posix/stubs.c \
@@ -44,6 +43,10 @@ ifdef CONFIG_NVGPU_FECS_TRACE
 srcs += os/posix/fecs_trace_posix.c
 endif
 
+ifeq ($(CONFIG_NVGPU_CLK_ARB),1)
+srcs += os/posix/posix-clk_arb.c
+endif
+
 ifdef CONFIG_NVGPU_NVLINK
 srcs +=	os/posix/posix-nvlink.c
 endif
@@ -143,8 +146,6 @@ srcs += common/utils/enabled.c \
 	common/fifo/pbdma_status.c \
 	common/fifo/userd.c \
 	common/mc/mc.c \
-	common/clk_arb/clk_arb.c \
-	common/clk_arb/clk_arb_gp10b.c \
 	common/fence/fence.c \
 	hal/mc/mc_gm20b.c  \
 	hal/mc/mc_gp10b.c  \
@@ -278,6 +279,12 @@ srcs += hal/init/hal_gp10b.c \
 	hal/mm/gmmu/gmmu_gm20b.c
 endif
 
+ifeq ($(CONFIG_NVGPU_CLK_ARB),1)
+srcs += \
+	common/clk_arb/clk_arb.c \
+	common/clk_arb/clk_arb_gp10b.c
+endif
+
 ifeq ($(CONFIG_NVGPU_ACR_LEGACY),1)
 srcs += \
 	common/acr/acr_blob_construct_v0.c \
@@ -424,12 +431,16 @@ srcs += \
 	common/pmu/pmu_debug.c \
 	common/pmu/pmu_mutex.c \
 	common/pmu/pmu_pstate.c \
-	common/clk_arb/clk_arb_gv100.c \
 	hal/therm/therm_tu104.c \
 	hal/pmu/pmu_gk20a.c \
 	hal/pmu/pmu_gm20b.c \
 	hal/pmu/pmu_gp10b.c \
 	hal/pmu/pmu_tu104.c
+
+ifeq ($(CONFIG_NVGPU_CLK_ARB),1)
+srcs += common/clk_arb/clk_arb_gv100.c
+endif
+
 endif
 
 ifeq ($(CONFIG_NVGPU_POWER_PG),1)

drivers/gpu/nvgpu/common/init/nvgpu_init.c

@@ -152,9 +152,11 @@ int gk20a_prepare_poweroff(struct gk20a *g)
 	if (g->ops.clk.suspend_clk_support != NULL) {
 		g->ops.clk.suspend_clk_support(g);
 	}
+#ifdef CONFIG_NVGPU_CLK_ARB
 	if (g->ops.clk_arb.stop_clk_arb_threads != NULL) {
 		g->ops.clk_arb.stop_clk_arb_threads(g);
 	}
+#endif
 	gk20a_mask_interrupts(g);
 
 	g->power_on = false;
@@ -454,11 +456,13 @@ int gk20a_finalize_poweron(struct gk20a *g)
 	} else
 #endif
 	{
+#ifdef CONFIG_NVGPU_CLK_ARB
 		err = nvgpu_clk_arb_init_arbiter(g);
 		if (err != 0) {
 			nvgpu_err(g, "failed to init clk arb");
 			goto done;
 		}
+#endif
 	}
 
 	err = nvgpu_init_therm_support(g);
@@ -628,12 +632,14 @@ void gk20a_init_gpu_characteristics(struct gk20a *g)
 
 	nvgpu_set_enabled(g, NVGPU_SUPPORT_TSG, true);
 
+#ifdef CONFIG_NVGPU_CLK_ARB
 	if (g->ops.clk_arb.check_clk_arb_support != NULL) {
 		if (g->ops.clk_arb.check_clk_arb_support(g)) {
 			nvgpu_set_enabled(g, NVGPU_SUPPORT_CLOCK_CONTROLS,
 					true);
 		}
 	}
+#endif
 
 	g->ops.gr.init.detect_sm_arch(g);
 

drivers/gpu/nvgpu/common/vgpu/clk_vgpu.c

@@ -38,6 +38,7 @@ static unsigned long vgpu_clk_get_rate(struct gk20a *g, u32 api_domain)
 	nvgpu_log_fn(g, " ");
 
 	switch (api_domain) {
+	case CTRL_CLK_DOMAIN_SYSCLK:
 	case CTRL_CLK_DOMAIN_GPCCLK:
 		msg.cmd = TEGRA_VGPU_CMD_GET_GPU_CLK_RATE;
 		msg.handle = vgpu_get_handle(g);

drivers/gpu/nvgpu/hal/gr/falcon/gr_falcon_gm20b.c

@@ -658,8 +658,8 @@ int gm20b_gr_falcon_wait_ctxsw_ready(struct gk20a *g)
 	}
 
 	if (nvgpu_platform_is_silicon(g)) {
-		if (g->ops.clk.measure_freq != NULL) {
+		if (g->ops.clk.get_rate != NULL) {
-			sysclk_freq_mhz = g->ops.clk.measure_freq(g,
+			sysclk_freq_mhz = g->ops.clk.get_rate(g,
 					CTRL_CLK_DOMAIN_SYSCLK) / MHZ;
 			if (sysclk_freq_mhz == 0UL) {
 				nvgpu_err(g, "failed to get SYSCLK freq");

drivers/gpu/nvgpu/hal/init/hal_gp10b.c

@@ -950,6 +950,7 @@ static const struct gpu_ops gp10b_ops = {
 		.pmu_ns_bootstrap = gk20a_pmu_ns_bootstrap,
 	},
 #endif
+#ifdef CONFIG_NVGPU_CLK_ARB
 	.clk_arb = {
 		.check_clk_arb_support = gp10b_check_clk_arb_support,
 		.get_arbiter_clk_domains = gp10b_get_arbiter_clk_domains,
@@ -960,6 +961,7 @@ static const struct gpu_ops gp10b_ops = {
 		.clk_arb_run_arbiter_cb = gp10b_clk_arb_run_arbiter_cb,
 		.clk_arb_cleanup = gp10b_clk_arb_cleanup,
 	},
+#endif
 #ifdef CONFIG_NVGPU_DEBUGGER
 	.regops = {
 		.exec_regops = exec_regops_gk20a,

drivers/gpu/nvgpu/hal/init/hal_gv11b.c

@@ -1117,6 +1117,7 @@ static const struct gpu_ops gv11b_ops = {
 		.pmu_ns_bootstrap = gv11b_pmu_bootstrap,
 #endif
 	},
+#ifdef CONFIG_NVGPU_CLK_ARB
 	.clk_arb = {
 		.check_clk_arb_support = gp10b_check_clk_arb_support,
 		.get_arbiter_clk_domains = gp10b_get_arbiter_clk_domains,
@@ -1127,6 +1128,7 @@ static const struct gpu_ops gv11b_ops = {
 		.clk_arb_run_arbiter_cb = gp10b_clk_arb_run_arbiter_cb,
 		.clk_arb_cleanup = gp10b_clk_arb_cleanup,
 	},
+#endif
 #ifdef CONFIG_NVGPU_DEBUGGER
 	.regops = {
 		.exec_regops = exec_regops_gk20a,
@@ -1345,7 +1347,9 @@ int gv11b_init_hal(struct gk20a *g)
 	gops->falcon = gv11b_ops.falcon;
 	gops->priv_ring = gv11b_ops.priv_ring;
 	gops->fuse = gv11b_ops.fuse;
+#ifdef CONFIG_NVGPU_CLK_ARB
 	gops->clk_arb = gv11b_ops.clk_arb;
+#endif
 	gops->top = gv11b_ops.top;
 
 	/* Lone functions */

drivers/gpu/nvgpu/hal/init/hal_tu104.c

@@ -1155,6 +1155,7 @@ static const struct gpu_ops tu104_ops = {
 		.clk_domain_get_f_points = gv100_clk_domain_get_f_points,
 		.get_maxrate = gv100_clk_maxrate,
 	},
+#ifdef CONFIG_NVGPU_CLK_ARB
 	.clk_arb = {
 		.check_clk_arb_support = gv100_check_clk_arb_support,
 		.get_arbiter_clk_domains = gv100_get_arbiter_clk_domains,
@@ -1168,6 +1169,7 @@ static const struct gpu_ops tu104_ops = {
 		.stop_clk_arb_threads = gv100_stop_clk_arb_threads,
 	},
 #endif
+#endif
 #ifdef CONFIG_NVGPU_DEBUGGER
 	.regops = {
 		.exec_regops = exec_regops_gk20a,
@@ -1497,7 +1499,9 @@ int tu104_init_hal(struct gk20a *g)
 	gops->clk.get_crystal_clk_hz = tu104_ops.clk.get_crystal_clk_hz;
 	gops->clk.measure_freq = tu104_ops.clk.measure_freq;
 	gops->clk.suspend_clk_support = tu104_ops.clk.suspend_clk_support;
+#ifdef CONFIG_NVGPU_CLK_ARB
 	gops->clk_arb = tu104_ops.clk_arb;
+#endif
 	gops->clk.clk_domain_get_f_points = tu104_ops.clk.clk_domain_get_f_points;
 	gops->clk = tu104_ops.clk;
 
@@ -1565,7 +1569,9 @@ int tu104_init_hal(struct gk20a *g)
 		gops->fb.mem_unlock = NULL;
 
 		/* Disable clock support */
+#ifdef CONFIG_NVGPU_CLK_ARB
 		gops->clk_arb.get_arbiter_clk_domains = NULL;
+#endif
 		gops->clk.support_clk_freq_controller = false;
 
 	} else

drivers/gpu/nvgpu/include/nvgpu/gk20a.h

@@ -64,7 +64,9 @@ struct nvgpu_gr_isr_data;
 struct nvgpu_gpu_ctxsw_trace_entry;
 struct nvgpu_cpu_time_correlation_sample;
 struct nvgpu_warpstate;
+#ifdef CONFIG_NVGPU_CLK_ARB
 struct nvgpu_clk_arb;
+#endif
 #ifdef CONFIG_NVGPU_FECS_TRACE
 struct nvgpu_gpu_ctxsw_trace_filter;
 #endif
@@ -1502,6 +1504,7 @@ struct gpu_ops {
 		bool support_vf_point;
 		u8 lut_num_entries;
 	} clk;
+#ifdef CONFIG_NVGPU_CLK_ARB
 	struct {
 		int (*arbiter_clk_init)(struct gk20a *g);
 		bool (*check_clk_arb_support)(struct gk20a *g);
@@ -1520,6 +1523,7 @@ struct gpu_ops {
 		void (*clk_arb_cleanup)(struct nvgpu_clk_arb *arb);
 		void (*stop_clk_arb_threads)(struct gk20a *g);
 	} clk_arb;
+#endif
 	struct {
 		int (*handle_pmu_perf_event)(struct gk20a *g, void *pmu_msg);
 		bool support_changeseq;

drivers/gpu/nvgpu/os/linux/clk.c

@@ -36,6 +36,7 @@ static unsigned long nvgpu_linux_clk_get_rate(struct gk20a *g, u32 api_domain)
 	unsigned long ret;
 
 	switch (api_domain) {
+	case CTRL_CLK_DOMAIN_SYSCLK:
 	case CTRL_CLK_DOMAIN_GPCCLK:
 		if (g->clk.tegra_clk)
 			ret = clk_get_rate(g->clk.tegra_clk);