diff --git a/arch/nvgpu-hal-new.yaml b/arch/nvgpu-hal-new.yaml index c9b660df5..c26dad4b1 100644 --- a/arch/nvgpu-hal-new.yaml +++ b/arch/nvgpu-hal-new.yaml @@ -1049,3 +1049,8 @@ grmgr: hal/grmgr/grmgr_ga100.c, hal/grmgr/grmgr_ga100.h,] +sim: + safe: no + owner: Antony Alex + sources: [ hal/sim/sim_ga10b.h, + hal/sim/sim_ga10b.c ] diff --git a/drivers/gpu/nvgpu/Makefile b/drivers/gpu/nvgpu/Makefile index f383eb1f8..abb5fcae6 100644 --- a/drivers/gpu/nvgpu/Makefile +++ b/drivers/gpu/nvgpu/Makefile @@ -867,7 +867,8 @@ nvgpu-y += \ hal/power_features/cg/ga10b_gating_reglist.o \ hal/therm/therm_ga10b_fusa.o \ hal/ce/ce_ga10b_fusa.o \ - hal/grmgr/grmgr_ga10b.o + hal/grmgr/grmgr_ga10b.o \ + hal/sim/sim_ga10b.o ifeq ($(CONFIG_NVGPU_COMPRESSION),y) nvgpu-y += \ diff --git a/drivers/gpu/nvgpu/Makefile.sources b/drivers/gpu/nvgpu/Makefile.sources index a47956a16..26461f5f2 100644 --- a/drivers/gpu/nvgpu/Makefile.sources +++ b/drivers/gpu/nvgpu/Makefile.sources @@ -786,7 +786,8 @@ srcs += hal/init/hal_ga10b.c \ hal/power_features/cg/ga10b_gating_reglist.c \ hal/therm/therm_ga10b_fusa.c \ hal/ce/ce_ga10b_fusa.c \ - hal/grmgr/grmgr_ga10b.c + hal/grmgr/grmgr_ga10b.c \ + hal/sim/sim_ga10b.c \ ifeq ($(CONFIG_NVGPU_COMPRESSION),1) srcs += \ diff --git a/drivers/gpu/nvgpu/common/acr/acr.c b/drivers/gpu/nvgpu/common/acr/acr.c index 17adb7d1c..3038cd312 100644 --- a/drivers/gpu/nvgpu/common/acr/acr.c +++ b/drivers/gpu/nvgpu/common/acr/acr.c @@ -147,7 +147,7 @@ int nvgpu_acr_init(struct gk20a *g) break; #if defined(CONFIG_NVGPU_NON_FUSA) case NVGPU_NEXT_GPUID: - nvgpu_next_acr_sw_init(g, g->acr); + nvgpu_ga10b_acr_sw_init(g, g->acr); break; #endif #ifdef CONFIG_NVGPU_DGPU @@ -156,7 +156,7 @@ int nvgpu_acr_init(struct gk20a *g) break; #if defined(CONFIG_NVGPU_NON_FUSA) case NVGPU_NEXT_DGPU_GPUID: - nvgpu_next_dgpu_acr_sw_init(g, g->acr); + nvgpu_ga100_acr_sw_init(g, g->acr); break; #endif #endif diff --git a/drivers/gpu/nvgpu/common/acr/acr_sw_ga100.c b/drivers/gpu/nvgpu/common/acr/acr_sw_ga100.c index c760988da..e0f5cffd0 100644 --- a/drivers/gpu/nvgpu/common/acr/acr_sw_ga100.c +++ b/drivers/gpu/nvgpu/common/acr/acr_sw_ga100.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2020, NVIDIA CORPORATION. All rights reserved. + * Copyright (c) 2020-2021, NVIDIA CORPORATION. All rights reserved. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), @@ -49,7 +49,7 @@ static u32* ga100_get_versioned_sig(struct gk20a *g, struct nvgpu_acr *acr, return sig; } -void nvgpu_next_dgpu_acr_sw_init(struct gk20a *g, struct nvgpu_acr *acr) +void nvgpu_ga100_acr_sw_init(struct gk20a *g, struct nvgpu_acr *acr) { nvgpu_log_fn(g, " "); diff --git a/drivers/gpu/nvgpu/common/acr/acr_sw_ga100.h b/drivers/gpu/nvgpu/common/acr/acr_sw_ga100.h index 04ea2da94..5fdf58992 100644 --- a/drivers/gpu/nvgpu/common/acr/acr_sw_ga100.h +++ b/drivers/gpu/nvgpu/common/acr/acr_sw_ga100.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2020, NVIDIA CORPORATION. All rights reserved. + * Copyright (c) 2020-2021, NVIDIA CORPORATION. All rights reserved. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), @@ -26,6 +26,6 @@ struct gk20a; struct nvgpu_acr; -void nvgpu_next_dgpu_acr_sw_init(struct gk20a *g, struct nvgpu_acr *acr); +void nvgpu_ga100_acr_sw_init(struct gk20a *g, struct nvgpu_acr *acr); #endif /*ACR_SW_GA100_H*/ diff --git a/drivers/gpu/nvgpu/common/acr/acr_sw_ga10b.c b/drivers/gpu/nvgpu/common/acr/acr_sw_ga10b.c index 97aa17d98..e9e99f4ca 100644 --- a/drivers/gpu/nvgpu/common/acr/acr_sw_ga10b.c +++ b/drivers/gpu/nvgpu/common/acr/acr_sw_ga10b.c @@ -312,7 +312,7 @@ static void ga10b_acr_sw_init(struct gk20a *g, struct nvgpu_acr *acr) acr->patch_wpr_info_to_ucode = ga10b_acr_patch_wpr_info_to_ucode; } -extern void nvgpu_next_acr_sw_init(struct gk20a *g, struct nvgpu_acr *acr) +extern void nvgpu_ga10b_acr_sw_init(struct gk20a *g, struct nvgpu_acr *acr) { nvgpu_log_fn(g, " "); acr->g = g; diff --git a/drivers/gpu/nvgpu/common/acr/acr_sw_ga10b.h b/drivers/gpu/nvgpu/common/acr/acr_sw_ga10b.h index 84f4e16e0..da241fecc 100644 --- a/drivers/gpu/nvgpu/common/acr/acr_sw_ga10b.h +++ b/drivers/gpu/nvgpu/common/acr/acr_sw_ga10b.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2020, NVIDIA CORPORATION. All rights reserved. + * Copyright (c) 2020-2021, NVIDIA CORPORATION. All rights reserved. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), @@ -26,6 +26,6 @@ struct gk20a; struct nvgpu_acr; -void nvgpu_next_acr_sw_init(struct gk20a *g, struct nvgpu_acr *acr); +void nvgpu_ga10b_acr_sw_init(struct gk20a *g, struct nvgpu_acr *acr); #endif /*ACR_SW_GA10B_H*/ diff --git a/drivers/gpu/nvgpu/common/cic/cic.c b/drivers/gpu/nvgpu/common/cic/cic.c index 2ab8c62fa..a109a1f51 100644 --- a/drivers/gpu/nvgpu/common/cic/cic.c +++ b/drivers/gpu/nvgpu/common/cic/cic.c @@ -173,7 +173,7 @@ void nvgpu_cic_intr_unit_vectorid_init(struct gk20a *g, u32 unit, u32 *vectorid, nvgpu_log(g, gpu_dbg_intr, "UNIT=%d, nvecs=%d", unit, num_entries); - intr_unit_info = g->mc.nvgpu_next.intr_unit_info; + intr_unit_info = g->mc.intr_unit_info; nvgpu_spinlock_irqsave(&g->mc.intr_lock, flags); @@ -198,7 +198,7 @@ bool nvgpu_cic_intr_is_unit_info_valid(struct gk20a *g, u32 unit) return false; } - intr_unit_info = g->mc.nvgpu_next.intr_unit_info; + intr_unit_info = g->mc.intr_unit_info; if (intr_unit_info[unit].valid == true) { info_valid = true; @@ -220,8 +220,8 @@ bool nvgpu_cic_intr_get_unit_info(struct gk20a *g, u32 unit, u32 *subtree, return false; } } - *subtree = g->mc.nvgpu_next.intr_unit_info[unit].subtree; - *subtree_mask = g->mc.nvgpu_next.intr_unit_info[unit].subtree_mask; + *subtree = g->mc.intr_unit_info[unit].subtree; + *subtree_mask = g->mc.intr_unit_info[unit].subtree_mask; nvgpu_log(g, gpu_dbg_intr, "subtree(%d) subtree_mask(%llx)", *subtree, *subtree_mask); diff --git a/drivers/gpu/nvgpu/common/falcon/falcon.c b/drivers/gpu/nvgpu/common/falcon/falcon.c index 59fd6add2..23f5db8a4 100644 --- a/drivers/gpu/nvgpu/common/falcon/falcon.c +++ b/drivers/gpu/nvgpu/common/falcon/falcon.c @@ -30,9 +30,9 @@ #include "falcon_sw_tu104.h" #endif -#if defined(CONFIG_NVGPU_NON_FUSA) +#ifdef CONFIG_NVGPU_NON_FUSA #include "nvgpu_next_gpuid.h" -#endif +#endif /* CONFIG_NVGPU_NON_FUSA */ static bool is_falcon_valid(struct nvgpu_falcon *flcn) { @@ -462,23 +462,19 @@ static int falcon_sw_chip_init(struct gk20a *g, struct nvgpu_falcon *flcn) case NVGPU_GPUID_GP10B: gk20a_falcon_sw_init(flcn); break; -#if defined(CONFIG_NVGPU_NON_FUSA) case NVGPU_NEXT_GPUID: - nvgpu_next_falcon_sw_init(flcn); - break; -#endif -#endif - case NVGPU_GPUID_GV11B: - gk20a_falcon_sw_init(flcn); + ga10b_falcon_sw_init(flcn); break; #ifdef CONFIG_NVGPU_DGPU case NVGPU_GPUID_TU104: -#if defined(CONFIG_NVGPU_NON_FUSA) case NVGPU_NEXT_DGPU_GPUID: -#endif tu104_falcon_sw_init(flcn); break; -#endif +#endif /* CONFIG_NVGPU_DGPU */ +#endif /* CONFIG_NVGPU_NON_FUSA */ + case NVGPU_GPUID_GV11B: + gk20a_falcon_sw_init(flcn); + break; default: err = -EINVAL; nvgpu_err(g, "no support for GPUID %x", ver); diff --git a/drivers/gpu/nvgpu/common/falcon/falcon_sw_ga10b.c b/drivers/gpu/nvgpu/common/falcon/falcon_sw_ga10b.c index 98c22efee..2ebb0c197 100644 --- a/drivers/gpu/nvgpu/common/falcon/falcon_sw_ga10b.c +++ b/drivers/gpu/nvgpu/common/falcon/falcon_sw_ga10b.c @@ -119,7 +119,7 @@ static void check_and_enable_falcon2(struct nvgpu_falcon *flcn, } } -extern void nvgpu_next_falcon_sw_init(struct nvgpu_falcon *flcn) +extern void ga10b_falcon_sw_init(struct nvgpu_falcon *flcn) { struct gk20a *g = flcn->g; diff --git a/drivers/gpu/nvgpu/common/falcon/falcon_sw_ga10b.h b/drivers/gpu/nvgpu/common/falcon/falcon_sw_ga10b.h index cafb9713a..6c7867288 100644 --- a/drivers/gpu/nvgpu/common/falcon/falcon_sw_ga10b.h +++ b/drivers/gpu/nvgpu/common/falcon/falcon_sw_ga10b.h @@ -1,6 +1,6 @@ /* - * Copyright (c) 2020, NVIDIA CORPORATION. All rights reserved. + * Copyright (c) 2020-2021, NVIDIA CORPORATION. All rights reserved. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), @@ -23,6 +23,6 @@ #ifndef NVGPU_FALCON_SW_GA10B_H #define NVGPU_FALCON_SW_GA10B_H -void nvgpu_next_falcon_sw_init(struct nvgpu_falcon *flcn); +void ga10b_falcon_sw_init(struct nvgpu_falcon *flcn); #endif /* NVGPU_FALCON_SW_GA10B_H */ diff --git a/drivers/gpu/nvgpu/common/fifo/engines.c b/drivers/gpu/nvgpu/common/fifo/engines.c index 45e712004..022d0d6b9 100644 --- a/drivers/gpu/nvgpu/common/fifo/engines.c +++ b/drivers/gpu/nvgpu/common/fifo/engines.c @@ -708,20 +708,13 @@ u32 nvgpu_engine_get_mask_on_id(struct gk20a *g, u32 id, bool is_tsg) #if defined(CONFIG_NVGPU_HAL_NON_FUSA) -int nvgpu_next_engine_init_one_dev(struct gk20a *g, - const struct nvgpu_device *dev) +int nvgpu_engine_init_one_dev_extra(struct gk20a *g, + const struct nvgpu_device *dev) { struct nvgpu_device *dev_rw = (struct nvgpu_device *)dev; /* - * Currently due to the nature of the nvgpu_next repo, this will still - * be called even on non-ga10b systems. Eventually this code will fold into - * the nvgpu-linux repo, at which point this logic will be present in - * nvgpu_engine_init_one_dev(). - * - * In any event, the purpose of this is to make sure we _don't_ execute - * this code pre-ga10b. We can check for HALs that only exist on ga10x to - * short circuit. + * Bail out on pre-ga10b platforms. */ if (g->ops.runlist.get_engine_id_from_rleng_id == NULL) { return 0; @@ -734,16 +727,16 @@ int nvgpu_next_engine_init_one_dev(struct gk20a *g, * See JIRA NVGPU-4980 for multiple pbdma support. */ g->ops.runlist.get_pbdma_info(g, - dev->next.rl_pri_base, - &dev_rw->next.pbdma_info); - if (dev->next.pbdma_info.pbdma_id[ENGINE_PBDMA_INSTANCE0] == + dev->rl_pri_base, + &dev_rw->pbdma_info); + if (dev->pbdma_info.pbdma_id[ENGINE_PBDMA_INSTANCE0] == NVGPU_INVALID_PBDMA_ID) { nvgpu_err(g, "busted pbdma info: no pbdma for engine id:%d", dev->engine_id); return -EINVAL; } - dev_rw->pbdma_id = dev->next.pbdma_info.pbdma_id[ENGINE_PBDMA_INSTANCE0]; + dev_rw->pbdma_id = dev->pbdma_info.pbdma_id[ENGINE_PBDMA_INSTANCE0]; nvgpu_log(g, gpu_dbg_device, "Parsed engine: ID: %u", dev->engine_id); nvgpu_log(g, gpu_dbg_device, " inst_id %u, runlist_id: %u, fault id %u", @@ -753,9 +746,9 @@ int nvgpu_next_engine_init_one_dev(struct gk20a *g, nvgpu_log(g, gpu_dbg_device, " engine_type %u", dev->type); nvgpu_log(g, gpu_dbg_device, " reset_id 0x%08x, rleng_id 0x%x", - dev->reset_id, dev->next.rleng_id); + dev->reset_id, dev->rleng_id); nvgpu_log(g, gpu_dbg_device, " runlist_pri_base 0x%x", - dev->next.rl_pri_base); + dev->rl_pri_base); return 0; } @@ -790,7 +783,10 @@ static int nvgpu_engine_init_one_dev(struct nvgpu_fifo *f, #if defined(CONFIG_NVGPU_NON_FUSA) { - int err = nvgpu_next_engine_init_one_dev(g, dev); + /* + * Fill Ampere+ device fields. + */ + int err = nvgpu_engine_init_one_dev_extra(g, dev); if (err != 0) { return err; } diff --git a/drivers/gpu/nvgpu/common/fifo/runlist.c b/drivers/gpu/nvgpu/common/fifo/runlist.c index ff532c018..aa0bd55ab 100644 --- a/drivers/gpu/nvgpu/common/fifo/runlist.c +++ b/drivers/gpu/nvgpu/common/fifo/runlist.c @@ -666,6 +666,66 @@ void nvgpu_runlist_cleanup_sw(struct gk20a *g) f->max_runlists = 0; } +#if defined(CONFIG_NVGPU_NON_FUSA) +static void nvgpu_runlist_init_engine_info(struct gk20a *g, + struct nvgpu_runlist *runlist, + const struct nvgpu_device *dev) +{ + u32 i = 0U; + + /* + * Bail out on pre-ga10b platforms. + */ + if (g->ops.runlist.get_engine_id_from_rleng_id == NULL) { + return; + } + + /* + * runlist_pri_base, chram_bar0_offset and pbdma_info + * will get over-written with same info, if multiple engines + * are present on same runlist. Required optimization will be + * done as part of JIRA NVGPU-4980 + */ + runlist->runlist_pri_base = + dev->rl_pri_base; + runlist->chram_bar0_offset = + g->ops.runlist.get_chram_bar0_offset(g, dev->rl_pri_base); + + nvgpu_log(g, gpu_dbg_info, "runlist[%d]: runlist_pri_base 0x%x", + runlist->id, runlist->runlist_pri_base); + nvgpu_log(g, gpu_dbg_info, "runlist[%d]: chram_bar0_offset 0x%x", + runlist->id, runlist->chram_bar0_offset); + + runlist->pbdma_info = &dev->pbdma_info; + for (i = 0U; i < PBDMA_PER_RUNLIST_SIZE; i++) { + nvgpu_log(g, gpu_dbg_info, + "runlist[%d]: pbdma_id[%d] %d pbdma_pri_base[%d] 0x%x", + runlist->id, i, + runlist->pbdma_info->pbdma_id[i], i, + runlist->pbdma_info->pbdma_pri_base[i]); + } + + runlist->rl_dev_list[dev->rleng_id] = dev; +} + +static u32 nvgpu_runlist_get_pbdma_mask(struct gk20a *g, + struct nvgpu_runlist *runlist) +{ + u32 pbdma_mask = 0U; + u32 i; + u32 pbdma_id; + + nvgpu_assert(runlist != NULL); + + for ( i = 0U; i < PBDMA_PER_RUNLIST_SIZE; i++) { + pbdma_id = runlist->pbdma_info->pbdma_id[i]; + if (pbdma_id != NVGPU_INVALID_PBDMA_ID) + pbdma_mask |= BIT32(pbdma_id); + } + return pbdma_mask; +} +#endif /* CONFIG_NVGPU_NON_FUSA */ + void nvgpu_runlist_init_enginfo(struct gk20a *g, struct nvgpu_fifo *f) { struct nvgpu_runlist *runlist; @@ -681,21 +741,44 @@ void nvgpu_runlist_init_enginfo(struct gk20a *g, struct nvgpu_fifo *f) for (i = 0; i < f->num_runlists; i++) { runlist = &f->active_runlists[i]; - (void) g->ops.fifo.find_pbdma_for_runlist(g, - runlist->id, - &runlist->pbdma_bitmask); - nvgpu_log(g, gpu_dbg_info, "runlist %d: pbdma bitmask 0x%x", - runlist->id, runlist->pbdma_bitmask); + nvgpu_log(g, gpu_dbg_info, "Configuring runlist %u (%u)", runlist->id, i); for (j = 0; j < f->num_engines; j++) { dev = f->active_engines[j]; if (dev->runlist_id == runlist->id) { runlist->eng_bitmask |= BIT32(dev->engine_id); +#ifdef CONFIG_NVGPU_NON_FUSA + /* + * Populate additional runlist fields on + * Ampere+ chips. + */ + nvgpu_runlist_init_engine_info(g, runlist, dev); +#endif /* CONFIG_NVGPU_NON_FUSA */ } } - nvgpu_log(g, gpu_dbg_info, "runlist %d: act eng bitmask 0x%x", - runlist->id, runlist->eng_bitmask); + + /* + * The PBDMA mask per runlist is probed differently on + * PreAmpere vs Ampere+ chips. + * + * Use legacy probing if g->ops.fifo.find_pbdma_for_runlist is + * assigned, else switch to new probe function + * nvgpu_runlist_get_pbdma_mask. + */ + if (g->ops.fifo.find_pbdma_for_runlist != NULL) { + (void) g->ops.fifo.find_pbdma_for_runlist(g, + runlist->id, + &runlist->pbdma_bitmask); + } +#ifdef CONFIG_NVGPU_NON_FUSA + else { + runlist->pbdma_bitmask = + nvgpu_runlist_get_pbdma_mask(g, runlist); + } +#endif /* CONFIG_NVGPU_NON_FUSA */ + nvgpu_log(g, gpu_dbg_info, " Active engine bitmask: 0x%x", runlist->eng_bitmask); + nvgpu_log(g, gpu_dbg_info, " PBDMA bitmask: 0x%x", runlist->pbdma_bitmask); } nvgpu_log_fn(g, "done"); @@ -913,92 +996,3 @@ void nvgpu_runlist_unlock_runlists(struct gk20a *g, u32 runlists_mask) } } } - -#if defined(CONFIG_NVGPU_NON_FUSA) -static void nvgpu_runlist_init_engine_info(struct gk20a *g, - struct nvgpu_runlist *runlist, - const struct nvgpu_device *dev) -{ - u32 i = 0U; - - /* - * runlist_pri_base, chram_bar0_offset and pbdma_info - * will get over-written with same info, if multiple engines - * are present on same runlist. Required optimization will be - * done as part of JIRA NVGPU-4980 - */ - runlist->nvgpu_next.runlist_pri_base = - dev->next.rl_pri_base; - runlist->nvgpu_next.chram_bar0_offset = - g->ops.runlist.get_chram_bar0_offset(g, dev->next.rl_pri_base); - - nvgpu_log(g, gpu_dbg_info, "runlist[%d]: runlist_pri_base 0x%x", - runlist->id, runlist->nvgpu_next.runlist_pri_base); - nvgpu_log(g, gpu_dbg_info, "runlist[%d]: chram_bar0_offset 0x%x", - runlist->id, runlist->nvgpu_next.chram_bar0_offset); - - runlist->nvgpu_next.pbdma_info = &dev->next.pbdma_info; - for (i = 0U; i < PBDMA_PER_RUNLIST_SIZE; i++) { - nvgpu_log(g, gpu_dbg_info, - "runlist[%d]: pbdma_id[%d] %d pbdma_pri_base[%d] 0x%x", - runlist->id, i, - runlist->nvgpu_next.pbdma_info->pbdma_id[i], i, - runlist->nvgpu_next.pbdma_info->pbdma_pri_base[i]); - } - - runlist->nvgpu_next.rl_dev_list[dev->next.rleng_id] = dev; -} - -static u32 nvgpu_runlist_get_pbdma_mask(struct gk20a *g, - struct nvgpu_runlist *runlist) -{ - u32 pbdma_mask = 0U; - u32 i; - u32 pbdma_id; - - nvgpu_assert(runlist != NULL); - - for ( i = 0U; i < PBDMA_PER_RUNLIST_SIZE; i++) { - pbdma_id = runlist->nvgpu_next.pbdma_info->pbdma_id[i]; - if (pbdma_id != NVGPU_INVALID_PBDMA_ID) - pbdma_mask |= BIT32(pbdma_id); - } - return pbdma_mask; -} - -void nvgpu_next_runlist_init_enginfo(struct gk20a *g, struct nvgpu_fifo *f) -{ - struct nvgpu_runlist *runlist; - const struct nvgpu_device *dev; - u32 i, j; - - nvgpu_log_fn(g, " "); - - if (g->is_virtual) { - return; - } - - for (i = 0U; i < f->num_runlists; i++) { - runlist = &f->active_runlists[i]; - - nvgpu_log(g, gpu_dbg_info, "Configuring runlist %u (%u)", runlist->id, i); - - for (j = 0U; j < f->num_engines; j++) { - dev = f->active_engines[j]; - - if (dev->runlist_id == runlist->id) { - runlist->eng_bitmask |= BIT32(dev->engine_id); - nvgpu_runlist_init_engine_info(g, runlist, dev); - } - } - - runlist->pbdma_bitmask = nvgpu_runlist_get_pbdma_mask(g, runlist); - - nvgpu_log(g, gpu_dbg_info, " Active engine bitmask: 0x%x", runlist->eng_bitmask); - nvgpu_log(g, gpu_dbg_info, " PBDMA bitmask: 0x%x", runlist->pbdma_bitmask); - } - - nvgpu_log_fn(g, "done"); -} -#endif - diff --git a/drivers/gpu/nvgpu/common/gr/gr.c b/drivers/gpu/nvgpu/common/gr/gr.c index 7702413b6..8ded4d0ab 100644 --- a/drivers/gpu/nvgpu/common/gr/gr.c +++ b/drivers/gpu/nvgpu/common/gr/gr.c @@ -1206,10 +1206,10 @@ void nvgpu_gr_init_reset_enable_hw_non_ctx_local(struct gk20a *g) { u32 i = 0U; struct netlist_av_list *sw_non_ctx_local_compute_load = - nvgpu_next_netlist_get_sw_non_ctx_local_compute_load_av_list(g); + nvgpu_netlist_get_sw_non_ctx_local_compute_load_av_list(g); #ifdef CONFIG_NVGPU_GRAPHICS struct netlist_av_list *sw_non_ctx_local_gfx_load = - nvgpu_next_netlist_get_sw_non_ctx_local_gfx_load_av_list(g); + nvgpu_netlist_get_sw_non_ctx_local_gfx_load_av_list(g); #endif for (i = 0U; i < sw_non_ctx_local_compute_load->count; i++) { @@ -1233,10 +1233,10 @@ void nvgpu_gr_init_reset_enable_hw_non_ctx_global(struct gk20a *g) { u32 i = 0U; struct netlist_av_list *sw_non_ctx_global_compute_load = - nvgpu_next_netlist_get_sw_non_ctx_global_compute_load_av_list(g); + nvgpu_netlist_get_sw_non_ctx_global_compute_load_av_list(g); #ifdef CONFIG_NVGPU_GRAPHICS struct netlist_av_list *sw_non_ctx_global_gfx_load = - nvgpu_next_netlist_get_sw_non_ctx_global_gfx_load_av_list(g); + nvgpu_netlist_get_sw_non_ctx_global_gfx_load_av_list(g); #endif for (i = 0U; i < sw_non_ctx_global_compute_load->count; i++) { diff --git a/drivers/gpu/nvgpu/common/netlist/netlist.c b/drivers/gpu/nvgpu/common/netlist/netlist.c index a30e3bafb..2076c2d44 100644 --- a/drivers/gpu/nvgpu/common/netlist/netlist.c +++ b/drivers/gpu/nvgpu/common/netlist/netlist.c @@ -209,15 +209,48 @@ static bool nvgpu_netlist_handle_sw_bundles_region_id(struct gk20a *g, err = nvgpu_netlist_alloc_load_av_list64(g, src, size, &netlist_vars->sw_bundle64_init); break; + +#if defined(CONFIG_NVGPU_NON_FUSA) + case NETLIST_REGIONID_SW_NON_CTX_LOCAL_COMPUTE_LOAD: + nvgpu_log_info(g, "NETLIST_REGIONID_SW_NON_CTX_LOCAL_COMPUTE_LOAD"); + err = nvgpu_netlist_alloc_load_av_list(g, src, size, + &netlist_vars->sw_non_ctx_local_compute_load); + break; + case NETLIST_REGIONID_SW_NON_CTX_GLOBAL_COMPUTE_LOAD: + nvgpu_log_info(g, "NETLIST_REGIONID_SW_NON_CTX_GLOBAL_COMPUTE_LOAD"); + err = nvgpu_netlist_alloc_load_av_list(g, src, size, + &netlist_vars->sw_non_ctx_global_compute_load); + break; +#endif + default: handled = false; -#if defined(CONFIG_NVGPU_NON_FUSA) - handled = nvgpu_next_netlist_handle_sw_bundles_region_id(g, - region_id, src, size, netlist_vars, &err); -#endif break; } +#if defined(CONFIG_NVGPU_NON_FUSA) + if ((handled == false) && (!nvgpu_is_enabled(g, NVGPU_SUPPORT_MIG))) { + handled = true; + switch (region_id) { +#ifdef CONFIG_NVGPU_GRAPHICS + case NETLIST_REGIONID_SW_NON_CTX_LOCAL_GFX_LOAD: + nvgpu_log_info(g, "NETLIST_REGIONID_SW_NON_CTX_LOCAL_GFX_LOAD"); + err = nvgpu_netlist_alloc_load_av_list(g, src, size, + &netlist_vars->sw_non_ctx_local_gfx_load); + break; + case NETLIST_REGIONID_SW_NON_CTX_GLOBAL_GFX_LOAD: + nvgpu_log_info(g, "NETLIST_REGIONID_SW_NON_CTX_GLOBAL_GFX_LOAD"); + err = nvgpu_netlist_alloc_load_av_list(g, src, size, + &netlist_vars->sw_non_ctx_global_gfx_load); + break; +#endif + default: + handled = false; + break; + } + } +#endif + *err_code = err; return handled; @@ -364,12 +397,52 @@ static bool nvgpu_netlist_handle_debugger_region_id(struct gk20a *g, err = nvgpu_netlist_alloc_load_aiv_list(g, src, size, &netlist_vars->ctxsw_regs.perf_pma_control); break; + +#if defined(CONFIG_NVGPU_NON_FUSA) + case NETLIST_REGIONID_CTXREG_SYS_COMPUTE: + nvgpu_log_info(g, "NETLIST_REGIONID_CTXREG_SYS_COMPUTE"); + err = nvgpu_netlist_alloc_load_aiv_list(g, src, size, + &netlist_vars->ctxsw_regs.sys_compute); + break; + + case NETLIST_REGIONID_CTXREG_GPC_COMPUTE: + nvgpu_log_info(g, "NETLIST_REGIONID_CTXREG_GPC_COMPUTE"); + err = nvgpu_netlist_alloc_load_aiv_list(g, src, size, + &netlist_vars->ctxsw_regs.gpc_compute); + break; + + case NETLIST_REGIONID_CTXREG_TPC_COMPUTE: + nvgpu_log_info(g, "NETLIST_REGIONID_CTXREG_TPC_COMPUTE"); + err = nvgpu_netlist_alloc_load_aiv_list(g, src, size, + &netlist_vars->ctxsw_regs.tpc_compute); + break; + + case NETLIST_REGIONID_CTXREG_PPC_COMPUTE: + nvgpu_log_info(g, "NETLIST_REGIONID_CTXREG_PPC_COMPUTE"); + err = nvgpu_netlist_alloc_load_aiv_list(g, src, size, + &netlist_vars->ctxsw_regs.ppc_compute); + break; + + case NETLIST_REGIONID_CTXREG_ETPC_COMPUTE: + nvgpu_log_info(g, "NETLIST_REGIONID_CTXREG_ETPC_COMPUTE"); + err = nvgpu_netlist_alloc_load_aiv_list(g, src, size, + &netlist_vars->ctxsw_regs.etpc_compute); + break; + case NETLIST_REGIONID_CTXREG_LTS_BC: + nvgpu_log_info(g, "NETLIST_REGIONID_CTXREG_LTS_BC"); + err = nvgpu_netlist_alloc_load_aiv_list(g, src, size, + &netlist_vars->ctxsw_regs.lts_bc); + break; + + case NETLIST_REGIONID_CTXREG_LTS_UC: + nvgpu_log_info(g, "NETLIST_REGIONID_CTXREG_LTS_UC"); + err = nvgpu_netlist_alloc_load_aiv_list(g, src, size, + &netlist_vars->ctxsw_regs.lts_uc); + break; +#endif + default: handled = false; -#if defined(CONFIG_NVGPU_NON_FUSA) - handled = nvgpu_next_netlist_handle_debugger_region_id(g, - region_id, src, size, netlist_vars, &err); -#endif break; } @@ -397,6 +470,31 @@ static bool nvgpu_netlist_handle_debugger_region_id(struct gk20a *g, err = nvgpu_netlist_alloc_load_aiv_list(g, src, size, &netlist_vars->ctxsw_regs.zcull_gpc); break; + case NETLIST_REGIONID_CTXREG_SYS_GFX: + nvgpu_log_info(g, "NETLIST_REGIONID_CTXREG_SYS_GFX"); + err = nvgpu_netlist_alloc_load_aiv_list(g, src, size, + &netlist_vars->ctxsw_regs.sys_gfx); + break; + case NETLIST_REGIONID_CTXREG_GPC_GFX: + nvgpu_log_info(g, "NETLIST_REGIONID_CTXREG_GPC_GFX"); + err = nvgpu_netlist_alloc_load_aiv_list(g, src, size, + &netlist_vars->ctxsw_regs.gpc_gfx); + break; + case NETLIST_REGIONID_CTXREG_TPC_GFX: + nvgpu_log_info(g, "NETLIST_REGIONID_CTXREG_TPC_GFX"); + err = nvgpu_netlist_alloc_load_aiv_list(g, src, size, + &netlist_vars->ctxsw_regs.tpc_gfx); + break; + case NETLIST_REGIONID_CTXREG_PPC_GFX: + nvgpu_log_info(g, "NETLIST_REGIONID_CTXREG_PPC_GFX"); + err = nvgpu_netlist_alloc_load_aiv_list(g, src, size, + &netlist_vars->ctxsw_regs.ppc_gfx); + break; + case NETLIST_REGIONID_CTXREG_ETPC_GFX: + nvgpu_log_info(g, "NETLIST_REGIONID_CTXREG_ETPC_GFX"); + err = nvgpu_netlist_alloc_load_aiv_list(g, src, size, + &netlist_vars->ctxsw_regs.etpc_gfx); + break; #endif case NETLIST_REGIONID_CTXREG_PPC: nvgpu_log_info(g, "NETLIST_REGIONID_CTXREG_PPC"); @@ -547,7 +645,12 @@ clean_up: nvgpu_kfree(g, netlist_vars->sw_ctx_load.l); nvgpu_kfree(g, netlist_vars->sw_non_ctx_load.l); #if defined(CONFIG_NVGPU_NON_FUSA) - nvgpu_next_netlist_deinit_ctx_vars(g); + nvgpu_kfree(g, netlist_vars->sw_non_ctx_local_compute_load.l); + nvgpu_kfree(g, netlist_vars->sw_non_ctx_global_compute_load.l); +#ifdef CONFIG_NVGPU_GRAPHICS + nvgpu_kfree(g, netlist_vars->sw_non_ctx_local_gfx_load.l); + nvgpu_kfree(g, netlist_vars->sw_non_ctx_global_gfx_load.l); +#endif #endif #ifdef CONFIG_NVGPU_DEBUGGER nvgpu_kfree(g, netlist_vars->ctxsw_regs.sys.l); @@ -574,7 +677,18 @@ clean_up: nvgpu_kfree(g, netlist_vars->ctxsw_regs.pm_ucgpc.l); nvgpu_kfree(g, netlist_vars->ctxsw_regs.etpc.l); #if defined(CONFIG_NVGPU_NON_FUSA) - nvgpu_next_netlist_deinit_ctxsw_regs(g); + nvgpu_kfree(g, netlist_vars->ctxsw_regs.sys_compute.l); + nvgpu_kfree(g, netlist_vars->ctxsw_regs.gpc_compute.l); + nvgpu_kfree(g, netlist_vars->ctxsw_regs.tpc_compute.l); + nvgpu_kfree(g, netlist_vars->ctxsw_regs.ppc_compute.l); + nvgpu_kfree(g, netlist_vars->ctxsw_regs.etpc_compute.l); + nvgpu_kfree(g, netlist_vars->ctxsw_regs.lts_bc.l); + nvgpu_kfree(g, netlist_vars->ctxsw_regs.lts_uc.l); + nvgpu_kfree(g, netlist_vars->ctxsw_regs.sys_gfx.l); + nvgpu_kfree(g, netlist_vars->ctxsw_regs.gpc_gfx.l); + nvgpu_kfree(g, netlist_vars->ctxsw_regs.tpc_gfx.l); + nvgpu_kfree(g, netlist_vars->ctxsw_regs.ppc_gfx.l); + nvgpu_kfree(g, netlist_vars->ctxsw_regs.etpc_gfx.l); #endif nvgpu_kfree(g, netlist_vars->ctxsw_regs.pm_cau.l); nvgpu_kfree(g, netlist_vars->ctxsw_regs.perf_sys_control.l); @@ -650,7 +764,12 @@ void nvgpu_netlist_deinit_ctx_vars(struct gk20a *g) nvgpu_kfree(g, netlist_vars->sw_ctx_load.l); nvgpu_kfree(g, netlist_vars->sw_non_ctx_load.l); #if defined(CONFIG_NVGPU_NON_FUSA) - nvgpu_next_netlist_deinit_ctx_vars(g); + nvgpu_kfree(g, netlist_vars->sw_non_ctx_local_compute_load.l); + nvgpu_kfree(g, netlist_vars->sw_non_ctx_global_compute_load.l); +#ifdef CONFIG_NVGPU_GRAPHICS + nvgpu_kfree(g, netlist_vars->sw_non_ctx_local_gfx_load.l); + nvgpu_kfree(g, netlist_vars->sw_non_ctx_global_gfx_load.l); +#endif #endif #ifdef CONFIG_NVGPU_DEBUGGER nvgpu_kfree(g, netlist_vars->ctxsw_regs.sys.l); @@ -676,7 +795,18 @@ void nvgpu_netlist_deinit_ctx_vars(struct gk20a *g) nvgpu_kfree(g, netlist_vars->ctxsw_regs.pm_rop.l); nvgpu_kfree(g, netlist_vars->ctxsw_regs.pm_ucgpc.l); #if defined(CONFIG_NVGPU_NON_FUSA) - nvgpu_next_netlist_deinit_ctxsw_regs(g); + nvgpu_kfree(g, netlist_vars->ctxsw_regs.sys_compute.l); + nvgpu_kfree(g, netlist_vars->ctxsw_regs.gpc_compute.l); + nvgpu_kfree(g, netlist_vars->ctxsw_regs.tpc_compute.l); + nvgpu_kfree(g, netlist_vars->ctxsw_regs.ppc_compute.l); + nvgpu_kfree(g, netlist_vars->ctxsw_regs.etpc_compute.l); + nvgpu_kfree(g, netlist_vars->ctxsw_regs.lts_bc.l); + nvgpu_kfree(g, netlist_vars->ctxsw_regs.lts_uc.l); + nvgpu_kfree(g, netlist_vars->ctxsw_regs.sys_gfx.l); + nvgpu_kfree(g, netlist_vars->ctxsw_regs.gpc_gfx.l); + nvgpu_kfree(g, netlist_vars->ctxsw_regs.tpc_gfx.l); + nvgpu_kfree(g, netlist_vars->ctxsw_regs.ppc_gfx.l); + nvgpu_kfree(g, netlist_vars->ctxsw_regs.etpc_gfx.l); #endif nvgpu_kfree(g, netlist_vars->ctxsw_regs.pm_cau.l); nvgpu_kfree(g, netlist_vars->ctxsw_regs.perf_sys_control.l); @@ -911,7 +1041,9 @@ u32 nvgpu_netlist_get_ppc_ctxsw_regs_count(struct gk20a *g) #if defined(CONFIG_NVGPU_NON_FUSA) if (count == 0U) { - count = nvgpu_next_netlist_get_ppc_ctxsw_regs_count(g); + count = nvgpu_netlist_get_ppc_compute_ctxsw_regs(g)->count; + count = nvgpu_safe_add_u32(count, + nvgpu_netlist_get_ppc_gfx_ctxsw_regs(g)->count); } #endif return count; @@ -923,7 +1055,9 @@ u32 nvgpu_netlist_get_gpc_ctxsw_regs_count(struct gk20a *g) #if defined(CONFIG_NVGPU_NON_FUSA) if (count == 0U) { - count = nvgpu_next_netlist_get_gpc_ctxsw_regs_count(g); + count = nvgpu_netlist_get_gpc_compute_ctxsw_regs(g)->count; + count = nvgpu_safe_add_u32(count, + nvgpu_netlist_get_gpc_gfx_ctxsw_regs(g)->count); } #endif return count; @@ -935,7 +1069,9 @@ u32 nvgpu_netlist_get_tpc_ctxsw_regs_count(struct gk20a *g) #if defined(CONFIG_NVGPU_NON_FUSA) if (count == 0U) { - count = nvgpu_next_netlist_get_tpc_ctxsw_regs_count(g); + count = nvgpu_netlist_get_tpc_compute_ctxsw_regs(g)->count; + count = nvgpu_safe_add_u32(count, + nvgpu_netlist_get_tpc_gfx_ctxsw_regs(g)->count); } #endif return count; @@ -947,7 +1083,9 @@ u32 nvgpu_netlist_get_etpc_ctxsw_regs_count(struct gk20a *g) #if defined(CONFIG_NVGPU_NON_FUSA) if (count == 0U) { - count = nvgpu_next_netlist_get_etpc_ctxsw_regs_count(g); + count = nvgpu_netlist_get_etpc_compute_ctxsw_regs(g)->count; + count = nvgpu_safe_add_u32(count, + nvgpu_netlist_get_etpc_gfx_ctxsw_regs(g)->count); } #endif return count; @@ -1009,7 +1147,23 @@ void nvgpu_netlist_print_ctxsw_reg_info(struct gk20a *g) nvgpu_log_info(g, "GRCTX_REG_LIST_PERF_PMA_CONTROL_COUNT :%d", nvgpu_netlist_get_perf_pma_control_ctxsw_regs(g)->count); #if defined(CONFIG_NVGPU_NON_FUSA) - nvgpu_next_netlist_print_ctxsw_reg_info(g); + nvgpu_log_info(g, "GRCTX_REG_LIST_SYS_(COMPUTE/GRAPICS)_COUNT :%d %d", + nvgpu_netlist_get_sys_compute_ctxsw_regs(g)->count, + nvgpu_netlist_get_sys_gfx_ctxsw_regs(g)->count); + nvgpu_log_info(g, "GRCTX_REG_LIST_GPC_(COMPUTE/GRAPHICS)_COUNT :%d %d", + nvgpu_netlist_get_gpc_compute_ctxsw_regs(g)->count, + nvgpu_netlist_get_gpc_gfx_ctxsw_regs(g)->count); + nvgpu_log_info(g, "GRCTX_REG_LIST_TPC_(COMPUTE/GRAPHICS)_COUNT :%d %d", + nvgpu_netlist_get_tpc_compute_ctxsw_regs(g)->count, + nvgpu_netlist_get_tpc_gfx_ctxsw_regs(g)->count); + nvgpu_log_info(g, "GRCTX_REG_LIST_PPC_(COMPUTE/GRAHPICS)_COUNT :%d %d", + nvgpu_netlist_get_ppc_compute_ctxsw_regs(g)->count, + nvgpu_netlist_get_ppc_gfx_ctxsw_regs(g)->count); + nvgpu_log_info(g, "GRCTX_REG_LIST_ETPC_(COMPUTE/GRAPHICS)_COUNT :%d %d", + nvgpu_netlist_get_etpc_compute_ctxsw_regs(g)->count, + nvgpu_netlist_get_etpc_gfx_ctxsw_regs(g)->count); + nvgpu_log_info(g, "GRCTX_REG_LIST_LTS_BC_COUNT :%d", + nvgpu_netlist_get_lts_ctxsw_regs(g)->count); #endif } @@ -1073,330 +1227,105 @@ void nvgpu_netlist_vars_set_regs_base_index(struct gk20a *g, u32 index) } #ifdef CONFIG_NVGPU_DEBUGGER -bool nvgpu_next_netlist_handle_debugger_region_id(struct gk20a *g, - u32 region_id, u8 *src, u32 size, - struct nvgpu_netlist_vars *netlist_vars, int *err_code) +struct netlist_aiv_list *nvgpu_netlist_get_sys_compute_ctxsw_regs( + struct gk20a *g) { - int err = 0; - bool handled = true; - - switch (region_id) { - case NETLIST_REGIONID_CTXREG_SYS_COMPUTE: - nvgpu_log_info(g, "NETLIST_REGIONID_CTXREG_SYS_COMPUTE"); - err = nvgpu_netlist_alloc_load_aiv_list(g, src, size, - &netlist_vars->ctxsw_regs.nvgpu_next.sys_compute); - break; - case NETLIST_REGIONID_CTXREG_GPC_COMPUTE: - nvgpu_log_info(g, "NETLIST_REGIONID_CTXREG_GPC_COMPUTE"); - err = nvgpu_netlist_alloc_load_aiv_list(g, src, size, - &netlist_vars->ctxsw_regs.nvgpu_next.gpc_compute); - break; - case NETLIST_REGIONID_CTXREG_TPC_COMPUTE: - nvgpu_log_info(g, "NETLIST_REGIONID_CTXREG_TPC_COMPUTE"); - err = nvgpu_netlist_alloc_load_aiv_list(g, src, size, - &netlist_vars->ctxsw_regs.nvgpu_next.tpc_compute); - break; - case NETLIST_REGIONID_CTXREG_PPC_COMPUTE: - nvgpu_log_info(g, "NETLIST_REGIONID_CTXREG_PPC_COMPUTE"); - err = nvgpu_netlist_alloc_load_aiv_list(g, src, size, - &netlist_vars->ctxsw_regs.nvgpu_next.ppc_compute); - break; - case NETLIST_REGIONID_CTXREG_ETPC_COMPUTE: - nvgpu_log_info(g, "NETLIST_REGIONID_CTXREG_ETPC_COMPUTE"); - err = nvgpu_netlist_alloc_load_aiv_list(g, src, size, - &netlist_vars->ctxsw_regs.nvgpu_next.etpc_compute); - break; - case NETLIST_REGIONID_CTXREG_LTS_BC: - nvgpu_log_info(g, "NETLIST_REGIONID_CTXREG_LTS_BC"); - err = nvgpu_netlist_alloc_load_aiv_list(g, src, size, - &netlist_vars->ctxsw_regs.nvgpu_next.lts_bc); - break; - case NETLIST_REGIONID_CTXREG_LTS_UC: - nvgpu_log_info(g, "NETLIST_REGIONID_CTXREG_LTS_UC"); - err = nvgpu_netlist_alloc_load_aiv_list(g, src, size, - &netlist_vars->ctxsw_regs.nvgpu_next.lts_uc); - break; - default: - handled = false; - break; - } - - if ((handled == false) && (!nvgpu_is_enabled(g, NVGPU_SUPPORT_MIG))) { - handled = true; - switch (region_id) { -#ifdef CONFIG_NVGPU_GRAPHICS - case NETLIST_REGIONID_CTXREG_SYS_GFX: - nvgpu_log_info(g, "NETLIST_REGIONID_CTXREG_SYS_GFX"); - err = nvgpu_netlist_alloc_load_aiv_list(g, src, size, - &netlist_vars->ctxsw_regs.nvgpu_next.sys_gfx); - break; - case NETLIST_REGIONID_CTXREG_GPC_GFX: - nvgpu_log_info(g, "NETLIST_REGIONID_CTXREG_GPC_GFX"); - err = nvgpu_netlist_alloc_load_aiv_list(g, src, size, - &netlist_vars->ctxsw_regs.nvgpu_next.gpc_gfx); - break; - case NETLIST_REGIONID_CTXREG_TPC_GFX: - nvgpu_log_info(g, "NETLIST_REGIONID_CTXREG_TPC_GFX"); - err = nvgpu_netlist_alloc_load_aiv_list(g, src, size, - &netlist_vars->ctxsw_regs.nvgpu_next.tpc_gfx); - break; - case NETLIST_REGIONID_CTXREG_PPC_GFX: - nvgpu_log_info(g, "NETLIST_REGIONID_CTXREG_PPC_GFX"); - err = nvgpu_netlist_alloc_load_aiv_list(g, src, size, - &netlist_vars->ctxsw_regs.nvgpu_next.ppc_gfx); - break; - case NETLIST_REGIONID_CTXREG_ETPC_GFX: - nvgpu_log_info(g, "NETLIST_REGIONID_CTXREG_ETPC_GFX"); - err = nvgpu_netlist_alloc_load_aiv_list(g, src, size, - &netlist_vars->ctxsw_regs.nvgpu_next.etpc_gfx); - break; -#endif - default: - handled = false; - break; - } - } - *err_code = err; - - return handled; + return &g->netlist_vars->ctxsw_regs.sys_compute; } -void nvgpu_next_netlist_deinit_ctxsw_regs(struct gk20a *g) +struct netlist_aiv_list *nvgpu_netlist_get_gpc_compute_ctxsw_regs( + struct gk20a *g) { - struct nvgpu_netlist_vars *netlist_vars = g->netlist_vars; + return &g->netlist_vars->ctxsw_regs.gpc_compute; +} - nvgpu_kfree(g, netlist_vars->ctxsw_regs.nvgpu_next.sys_compute.l); - nvgpu_kfree(g, netlist_vars->ctxsw_regs.nvgpu_next.gpc_compute.l); - nvgpu_kfree(g, netlist_vars->ctxsw_regs.nvgpu_next.tpc_compute.l); - nvgpu_kfree(g, netlist_vars->ctxsw_regs.nvgpu_next.ppc_compute.l); - nvgpu_kfree(g, netlist_vars->ctxsw_regs.nvgpu_next.etpc_compute.l); - nvgpu_kfree(g, netlist_vars->ctxsw_regs.nvgpu_next.lts_bc.l); - nvgpu_kfree(g, netlist_vars->ctxsw_regs.nvgpu_next.lts_uc.l); - nvgpu_kfree(g, netlist_vars->ctxsw_regs.nvgpu_next.sys_gfx.l); - nvgpu_kfree(g, netlist_vars->ctxsw_regs.nvgpu_next.gpc_gfx.l); - nvgpu_kfree(g, netlist_vars->ctxsw_regs.nvgpu_next.tpc_gfx.l); - nvgpu_kfree(g, netlist_vars->ctxsw_regs.nvgpu_next.ppc_gfx.l); - nvgpu_kfree(g, netlist_vars->ctxsw_regs.nvgpu_next.etpc_gfx.l); +struct netlist_aiv_list *nvgpu_netlist_get_tpc_compute_ctxsw_regs( + struct gk20a *g) +{ + return &g->netlist_vars->ctxsw_regs.tpc_compute; +} + +struct netlist_aiv_list *nvgpu_netlist_get_ppc_compute_ctxsw_regs( + struct gk20a *g) +{ + return &g->netlist_vars->ctxsw_regs.ppc_compute; +} + +struct netlist_aiv_list *nvgpu_netlist_get_etpc_compute_ctxsw_regs( + struct gk20a *g) +{ + return &g->netlist_vars->ctxsw_regs.etpc_compute; +} + +struct netlist_aiv_list *nvgpu_netlist_get_lts_ctxsw_regs( + struct gk20a *g) +{ + return &g->netlist_vars->ctxsw_regs.lts_bc; +} + +struct netlist_aiv_list *nvgpu_netlist_get_sys_gfx_ctxsw_regs( + struct gk20a *g) +{ + return &g->netlist_vars->ctxsw_regs.sys_gfx; +} + +struct netlist_aiv_list *nvgpu_netlist_get_gpc_gfx_ctxsw_regs( + struct gk20a *g) +{ + return &g->netlist_vars->ctxsw_regs.gpc_gfx; +} + +struct netlist_aiv_list *nvgpu_netlist_get_tpc_gfx_ctxsw_regs( + struct gk20a *g) +{ + return &g->netlist_vars->ctxsw_regs.tpc_gfx; +} + +struct netlist_aiv_list *nvgpu_netlist_get_ppc_gfx_ctxsw_regs( + struct gk20a *g) +{ + return &g->netlist_vars->ctxsw_regs.ppc_gfx; +} + +struct netlist_aiv_list *nvgpu_netlist_get_etpc_gfx_ctxsw_regs( + struct gk20a *g) +{ + return &g->netlist_vars->ctxsw_regs.etpc_gfx; +} + +u32 nvgpu_netlist_get_sys_ctxsw_regs_count(struct gk20a *g) +{ + u32 count = nvgpu_netlist_get_sys_compute_ctxsw_regs(g)->count; + + count = nvgpu_safe_add_u32(count, + nvgpu_netlist_get_sys_gfx_ctxsw_regs(g)->count); + return count; } #endif /* CONFIG_NVGPU_DEBUGGER */ -bool nvgpu_next_netlist_handle_sw_bundles_region_id(struct gk20a *g, - u32 region_id, u8 *src, u32 size, - struct nvgpu_netlist_vars *netlist_vars, int *err_code) -{ - int err = 0; - bool handled = true; - - switch(region_id) { - case NETLIST_REGIONID_SW_NON_CTX_LOCAL_COMPUTE_LOAD: - nvgpu_log_info(g, "NETLIST_REGIONID_SW_NON_CTX_LOCAL_COMPUTE_LOAD"); - err = nvgpu_netlist_alloc_load_av_list(g, src, size, - &netlist_vars->nvgpu_next.sw_non_ctx_local_compute_load); - break; - case NETLIST_REGIONID_SW_NON_CTX_GLOBAL_COMPUTE_LOAD: - nvgpu_log_info(g, "NETLIST_REGIONID_SW_NON_CTX_GLOBAL_COMPUTE_LOAD"); - err = nvgpu_netlist_alloc_load_av_list(g, src, size, - &netlist_vars->nvgpu_next.sw_non_ctx_global_compute_load); - break; - default: - handled = false; - break; - } - - if ((handled == false) && (!nvgpu_is_enabled(g, NVGPU_SUPPORT_MIG))) { - handled = true; - switch (region_id) { -#ifdef CONFIG_NVGPU_GRAPHICS - case NETLIST_REGIONID_SW_NON_CTX_LOCAL_GFX_LOAD: - nvgpu_log_info(g, "NETLIST_REGIONID_SW_NON_CTX_LOCAL_GFX_LOAD"); - err = nvgpu_netlist_alloc_load_av_list(g, src, size, - &netlist_vars->nvgpu_next.sw_non_ctx_local_gfx_load); - break; - case NETLIST_REGIONID_SW_NON_CTX_GLOBAL_GFX_LOAD: - nvgpu_log_info(g, "NETLIST_REGIONID_SW_NON_CTX_GLOBAL_GFX_LOAD"); - err = nvgpu_netlist_alloc_load_av_list(g, src, size, - &netlist_vars->nvgpu_next.sw_non_ctx_global_gfx_load); - break; -#endif - default: - handled = false; - break; - } - } - *err_code = err; - - return handled; -} - -void nvgpu_next_netlist_deinit_ctx_vars(struct gk20a *g) -{ - struct nvgpu_netlist_vars *netlist_vars = g->netlist_vars; - - nvgpu_kfree(g, netlist_vars->nvgpu_next.sw_non_ctx_local_compute_load.l); - nvgpu_kfree(g, netlist_vars->nvgpu_next.sw_non_ctx_global_compute_load.l); -#ifdef CONFIG_NVGPU_GRAPHICS - nvgpu_kfree(g, netlist_vars->nvgpu_next.sw_non_ctx_local_gfx_load.l); - nvgpu_kfree(g, netlist_vars->nvgpu_next.sw_non_ctx_global_gfx_load.l); -#endif -} - -#ifdef CONFIG_NVGPU_DEBUGGER -struct netlist_aiv_list *nvgpu_next_netlist_get_sys_compute_ctxsw_regs( +struct netlist_av_list *nvgpu_netlist_get_sw_non_ctx_local_compute_load_av_list( struct gk20a *g) { - return &g->netlist_vars->ctxsw_regs.nvgpu_next.sys_compute; + return &g->netlist_vars->sw_non_ctx_local_compute_load; } -struct netlist_aiv_list *nvgpu_next_netlist_get_gpc_compute_ctxsw_regs( +struct netlist_av_list *nvgpu_netlist_get_sw_non_ctx_global_compute_load_av_list( struct gk20a *g) { - return &g->netlist_vars->ctxsw_regs.nvgpu_next.gpc_compute; -} - -struct netlist_aiv_list *nvgpu_next_netlist_get_tpc_compute_ctxsw_regs( - struct gk20a *g) -{ - return &g->netlist_vars->ctxsw_regs.nvgpu_next.tpc_compute; -} - -struct netlist_aiv_list *nvgpu_next_netlist_get_ppc_compute_ctxsw_regs( - struct gk20a *g) -{ - return &g->netlist_vars->ctxsw_regs.nvgpu_next.ppc_compute; -} - -struct netlist_aiv_list *nvgpu_next_netlist_get_etpc_compute_ctxsw_regs( - struct gk20a *g) -{ - return &g->netlist_vars->ctxsw_regs.nvgpu_next.etpc_compute; -} - -struct netlist_aiv_list *nvgpu_next_netlist_get_lts_ctxsw_regs( - struct gk20a *g) -{ - return &g->netlist_vars->ctxsw_regs.nvgpu_next.lts_bc; -} - -struct netlist_aiv_list *nvgpu_next_netlist_get_sys_gfx_ctxsw_regs( - struct gk20a *g) -{ - return &g->netlist_vars->ctxsw_regs.nvgpu_next.sys_gfx; -} - -struct netlist_aiv_list *nvgpu_next_netlist_get_gpc_gfx_ctxsw_regs( - struct gk20a *g) -{ - return &g->netlist_vars->ctxsw_regs.nvgpu_next.gpc_gfx; -} - -struct netlist_aiv_list *nvgpu_next_netlist_get_tpc_gfx_ctxsw_regs( - struct gk20a *g) -{ - return &g->netlist_vars->ctxsw_regs.nvgpu_next.tpc_gfx; -} - -struct netlist_aiv_list *nvgpu_next_netlist_get_ppc_gfx_ctxsw_regs( - struct gk20a *g) -{ - return &g->netlist_vars->ctxsw_regs.nvgpu_next.ppc_gfx; -} - -struct netlist_aiv_list *nvgpu_next_netlist_get_etpc_gfx_ctxsw_regs( - struct gk20a *g) -{ - return &g->netlist_vars->ctxsw_regs.nvgpu_next.etpc_gfx; -} - -u32 nvgpu_next_netlist_get_sys_ctxsw_regs_count(struct gk20a *g) -{ - u32 count = nvgpu_next_netlist_get_sys_compute_ctxsw_regs(g)->count; - - count = nvgpu_safe_add_u32(count, - nvgpu_next_netlist_get_sys_gfx_ctxsw_regs(g)->count); - return count; -} - -u32 nvgpu_next_netlist_get_ppc_ctxsw_regs_count(struct gk20a *g) -{ - u32 count = nvgpu_next_netlist_get_ppc_compute_ctxsw_regs(g)->count; - - count = nvgpu_safe_add_u32(count, - nvgpu_next_netlist_get_ppc_gfx_ctxsw_regs(g)->count); - return count; -} - -u32 nvgpu_next_netlist_get_gpc_ctxsw_regs_count(struct gk20a *g) -{ - u32 count = nvgpu_next_netlist_get_gpc_compute_ctxsw_regs(g)->count; - - count = nvgpu_safe_add_u32(count, - nvgpu_next_netlist_get_gpc_gfx_ctxsw_regs(g)->count); - return count; -} - -u32 nvgpu_next_netlist_get_tpc_ctxsw_regs_count(struct gk20a *g) -{ - u32 count = nvgpu_next_netlist_get_tpc_compute_ctxsw_regs(g)->count; - - count = nvgpu_safe_add_u32(count, - nvgpu_next_netlist_get_tpc_gfx_ctxsw_regs(g)->count); - return count; -} - -u32 nvgpu_next_netlist_get_etpc_ctxsw_regs_count(struct gk20a *g) -{ - u32 count = nvgpu_next_netlist_get_etpc_compute_ctxsw_regs(g)->count; - - count = nvgpu_safe_add_u32(count, - nvgpu_next_netlist_get_etpc_gfx_ctxsw_regs(g)->count); - return count; -} - -void nvgpu_next_netlist_print_ctxsw_reg_info(struct gk20a *g) -{ - nvgpu_log_info(g, "GRCTX_REG_LIST_SYS_(COMPUTE/GRAPICS)_COUNT :%d %d", - nvgpu_next_netlist_get_sys_compute_ctxsw_regs(g)->count, - nvgpu_next_netlist_get_sys_gfx_ctxsw_regs(g)->count); - nvgpu_log_info(g, "GRCTX_REG_LIST_GPC_(COMPUTE/GRAPHICS)_COUNT :%d %d", - nvgpu_next_netlist_get_gpc_compute_ctxsw_regs(g)->count, - nvgpu_next_netlist_get_gpc_gfx_ctxsw_regs(g)->count); - nvgpu_log_info(g, "GRCTX_REG_LIST_TPC_(COMPUTE/GRAPHICS)_COUNT :%d %d", - nvgpu_next_netlist_get_tpc_compute_ctxsw_regs(g)->count, - nvgpu_next_netlist_get_tpc_gfx_ctxsw_regs(g)->count); - nvgpu_log_info(g, "GRCTX_REG_LIST_PPC_(COMPUTE/GRAHPICS)_COUNT :%d %d", - nvgpu_next_netlist_get_ppc_compute_ctxsw_regs(g)->count, - nvgpu_next_netlist_get_ppc_gfx_ctxsw_regs(g)->count); - nvgpu_log_info(g, "GRCTX_REG_LIST_ETPC_(COMPUTE/GRAPHICS)_COUNT :%d %d", - nvgpu_next_netlist_get_etpc_compute_ctxsw_regs(g)->count, - nvgpu_next_netlist_get_etpc_gfx_ctxsw_regs(g)->count); - nvgpu_log_info(g, "GRCTX_REG_LIST_LTS_BC_COUNT :%d", - nvgpu_next_netlist_get_lts_ctxsw_regs(g)->count); -} -#endif /* CONFIG_NVGPU_DEBUGGER */ - -struct netlist_av_list *nvgpu_next_netlist_get_sw_non_ctx_local_compute_load_av_list( - struct gk20a *g) -{ - return &g->netlist_vars->nvgpu_next.sw_non_ctx_local_compute_load; -} - -struct netlist_av_list *nvgpu_next_netlist_get_sw_non_ctx_global_compute_load_av_list( - struct gk20a *g) -{ - return &g->netlist_vars->nvgpu_next.sw_non_ctx_global_compute_load; + return &g->netlist_vars->sw_non_ctx_global_compute_load; } #ifdef CONFIG_NVGPU_GRAPHICS -struct netlist_av_list *nvgpu_next_netlist_get_sw_non_ctx_local_gfx_load_av_list( +struct netlist_av_list *nvgpu_netlist_get_sw_non_ctx_local_gfx_load_av_list( struct gk20a *g) { - return &g->netlist_vars->nvgpu_next.sw_non_ctx_local_gfx_load; + return &g->netlist_vars->sw_non_ctx_local_gfx_load; } -struct netlist_av_list *nvgpu_next_netlist_get_sw_non_ctx_global_gfx_load_av_list( +struct netlist_av_list *nvgpu_netlist_get_sw_non_ctx_global_gfx_load_av_list( struct gk20a *g) { - return &g->netlist_vars->nvgpu_next.sw_non_ctx_global_gfx_load; + return &g->netlist_vars->sw_non_ctx_global_gfx_load; } #endif /* CONFIG_NVGPU_GRAPHICS */ diff --git a/drivers/gpu/nvgpu/common/netlist/netlist_priv.h b/drivers/gpu/nvgpu/common/netlist/netlist_priv.h index 5d7dfabd6..40f1a88e0 100644 --- a/drivers/gpu/nvgpu/common/netlist/netlist_priv.h +++ b/drivers/gpu/nvgpu/common/netlist/netlist_priv.h @@ -123,37 +123,6 @@ struct netlist_gr_ucode { } gpccs, fecs; }; - -#if defined(CONFIG_NVGPU_HAL_NON_FUSA) -struct nvgpu_next_netlist_vars { - struct netlist_av_list sw_non_ctx_local_compute_load; - struct netlist_av_list sw_non_ctx_global_compute_load; -#ifdef CONFIG_NVGPU_GRAPHICS - struct netlist_av_list sw_non_ctx_local_gfx_load; - struct netlist_av_list sw_non_ctx_global_gfx_load; -#endif /* CONFIG_NVGPU_GRAPHICS */ -}; - -#ifdef CONFIG_NVGPU_DEBUGGER -struct nvgpu_next_ctxsw_regs { - struct netlist_aiv_list sys_compute; - struct netlist_aiv_list gpc_compute; - struct netlist_aiv_list tpc_compute; - struct netlist_aiv_list ppc_compute; - struct netlist_aiv_list etpc_compute; - struct netlist_aiv_list lts_bc; - struct netlist_aiv_list lts_uc; -#ifdef CONFIG_NVGPU_GRAPHICS - struct netlist_aiv_list sys_gfx; - struct netlist_aiv_list gpc_gfx; - struct netlist_aiv_list tpc_gfx; - struct netlist_aiv_list ppc_gfx; - struct netlist_aiv_list etpc_gfx; -#endif /* CONFIG_NVGPU_GRAPHICS */ -}; -#endif /* CONFIG_NVGPU_DEBUGGER */ - -#endif /* CONFIG_NVGPU_HAL_NON_FUSA */ struct nvgpu_netlist_vars { bool dynamic; @@ -168,7 +137,12 @@ struct nvgpu_netlist_vars { struct netlist_aiv_list sw_ctx_load; struct netlist_av_list sw_non_ctx_load; #if defined(CONFIG_NVGPU_NON_FUSA) - struct nvgpu_next_netlist_vars nvgpu_next; + struct netlist_av_list sw_non_ctx_local_compute_load; + struct netlist_av_list sw_non_ctx_global_compute_load; +#ifdef CONFIG_NVGPU_GRAPHICS + struct netlist_av_list sw_non_ctx_local_gfx_load; + struct netlist_av_list sw_non_ctx_global_gfx_load; +#endif /* CONFIG_NVGPU_GRAPHICS */ #endif struct netlist_av_list sw_veid_bundle_init; #ifdef CONFIG_NVGPU_DEBUGGER @@ -202,8 +176,21 @@ struct nvgpu_netlist_vars { struct netlist_aiv_list perf_gpc_control; struct netlist_aiv_list perf_pma_control; #if defined(CONFIG_NVGPU_NON_FUSA) - struct nvgpu_next_ctxsw_regs nvgpu_next; -#endif + struct netlist_aiv_list sys_compute; + struct netlist_aiv_list gpc_compute; + struct netlist_aiv_list tpc_compute; + struct netlist_aiv_list ppc_compute; + struct netlist_aiv_list etpc_compute; + struct netlist_aiv_list lts_bc; + struct netlist_aiv_list lts_uc; +#ifdef CONFIG_NVGPU_GRAPHICS + struct netlist_aiv_list sys_gfx; + struct netlist_aiv_list gpc_gfx; + struct netlist_aiv_list tpc_gfx; + struct netlist_aiv_list ppc_gfx; + struct netlist_aiv_list etpc_gfx; +#endif /* CONFIG_NVGPU_GRAPHICS */ +#endif /* CONFIG_NVGPU_NON_FUSA */ } ctxsw_regs; #endif /* CONFIG_NVGPU_DEBUGGER */ }; diff --git a/drivers/gpu/nvgpu/common/pmu/perfmon/pmu_perfmon.c b/drivers/gpu/nvgpu/common/pmu/perfmon/pmu_perfmon.c index 6438ae3ed..3cdaa7ae6 100644 --- a/drivers/gpu/nvgpu/common/pmu/perfmon/pmu_perfmon.c +++ b/drivers/gpu/nvgpu/common/pmu/perfmon/pmu_perfmon.c @@ -146,7 +146,7 @@ int nvgpu_pmu_initialize_perfmon(struct gk20a *g, struct nvgpu_pmu *pmu, break; #if defined(CONFIG_NVGPU_NON_FUSA) case NVGPU_NEXT_GPUID: - nvgpu_next_perfmon_sw_init(g, *perfmon_ptr); + nvgpu_ga10b_perfmon_sw_init(g, *perfmon_ptr); break; #endif default: diff --git a/drivers/gpu/nvgpu/common/pmu/perfmon/pmu_perfmon_sw_ga10b.c b/drivers/gpu/nvgpu/common/pmu/perfmon/pmu_perfmon_sw_ga10b.c index e5c234801..f4a54c0e7 100644 --- a/drivers/gpu/nvgpu/common/pmu/perfmon/pmu_perfmon_sw_ga10b.c +++ b/drivers/gpu/nvgpu/common/pmu/perfmon/pmu_perfmon_sw_ga10b.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2020, NVIDIA CORPORATION. All rights reserved. + * Copyright (c) 2020-2021, NVIDIA CORPORATION. All rights reserved. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), @@ -25,7 +25,7 @@ #include "pmu_perfmon_sw_ga10b.h" -void nvgpu_next_perfmon_sw_init(struct gk20a *g, +void nvgpu_ga10b_perfmon_sw_init(struct gk20a *g, struct nvgpu_pmu_perfmon *perfmon) { nvgpu_log_fn(g, " "); diff --git a/drivers/gpu/nvgpu/common/pmu/perfmon/pmu_perfmon_sw_ga10b.h b/drivers/gpu/nvgpu/common/pmu/perfmon/pmu_perfmon_sw_ga10b.h index 238a256fc..2b24bd152 100644 --- a/drivers/gpu/nvgpu/common/pmu/perfmon/pmu_perfmon_sw_ga10b.h +++ b/drivers/gpu/nvgpu/common/pmu/perfmon/pmu_perfmon_sw_ga10b.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2020, NVIDIA CORPORATION. All rights reserved. + * Copyright (c) 2020-2021, NVIDIA CORPORATION. All rights reserved. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), @@ -23,7 +23,7 @@ #ifndef NVGPU_PMU_PERFMON_SW_GA10B_H #define NVGPU_PMU_PERFMON_SW_GA10B_H -void nvgpu_next_perfmon_sw_init(struct gk20a *g, +void nvgpu_ga10b_perfmon_sw_init(struct gk20a *g, struct nvgpu_pmu_perfmon *perfmon); #endif /* NVGPU_PMU_PERFMON_SW_GA10B_H */ diff --git a/drivers/gpu/nvgpu/common/pmu/pg/pg_sw_ga10b.c b/drivers/gpu/nvgpu/common/pmu/pg/pg_sw_ga10b.c index b3db96c1b..ed7a558d1 100644 --- a/drivers/gpu/nvgpu/common/pmu/pg/pg_sw_ga10b.c +++ b/drivers/gpu/nvgpu/common/pmu/pg/pg_sw_ga10b.c @@ -357,7 +357,7 @@ static int ga10b_pmu_elpg_statistics(struct gk20a *g, u32 pg_engine_id, return err; } -void nvgpu_next_pg_sw_init(struct gk20a *g, +void nvgpu_ga10b_pg_sw_init(struct gk20a *g, struct nvgpu_pmu_pg *pg) { nvgpu_log_fn(g, " "); diff --git a/drivers/gpu/nvgpu/common/pmu/pg/pg_sw_ga10b.h b/drivers/gpu/nvgpu/common/pmu/pg/pg_sw_ga10b.h index 2958760b9..05bc90d42 100644 --- a/drivers/gpu/nvgpu/common/pmu/pg/pg_sw_ga10b.h +++ b/drivers/gpu/nvgpu/common/pmu/pg/pg_sw_ga10b.h @@ -292,7 +292,7 @@ struct pmu_pg_stats_v3 u32 hw_disallow_reason_mask; }; -void nvgpu_next_pg_sw_init(struct gk20a *g, struct nvgpu_pmu_pg *pg); +void nvgpu_ga10b_pg_sw_init(struct gk20a *g, struct nvgpu_pmu_pg *pg); u32 ga10b_pmu_pg_engines_list(struct gk20a *g); #endif /* NVGPU_PMU_PG_SW_GA10B_H */ diff --git a/drivers/gpu/nvgpu/common/pmu/pg/pmu_pg.c b/drivers/gpu/nvgpu/common/pmu/pg/pmu_pg.c index c4d809e46..5b25f78d4 100644 --- a/drivers/gpu/nvgpu/common/pmu/pg/pmu_pg.c +++ b/drivers/gpu/nvgpu/common/pmu/pg/pmu_pg.c @@ -882,7 +882,7 @@ int nvgpu_pmu_pg_init(struct gk20a *g, struct nvgpu_pmu *pmu, #if defined(CONFIG_NVGPU_NON_FUSA) case NVGPU_NEXT_GPUID: - nvgpu_next_pg_sw_init(g, *pg_p); + nvgpu_ga10b_pg_sw_init(g, *pg_p); break; #endif diff --git a/drivers/gpu/nvgpu/common/profiler/profiler.c b/drivers/gpu/nvgpu/common/profiler/profiler.c index 6bbc848bc..210bee226 100644 --- a/drivers/gpu/nvgpu/common/profiler/profiler.c +++ b/drivers/gpu/nvgpu/common/profiler/profiler.c @@ -1159,7 +1159,7 @@ bool nvgpu_profiler_validate_regops_allowlist(struct nvgpu_profiler_object *prof } #ifdef CONFIG_NVGPU_HAL_NON_FUSA -void nvgpu_next_profiler_hs_stream_quiesce(struct gk20a *g) +void nvgpu_profiler_hs_stream_quiesce(struct gk20a *g) { if (g->ops.perf.reset_hs_streaming_credits != NULL) { /* Reset high speed streaming credits to 0. */ diff --git a/drivers/gpu/nvgpu/common/sim/sim.c b/drivers/gpu/nvgpu/common/sim/sim.c index cff8871a9..34e9b5d20 100644 --- a/drivers/gpu/nvgpu/common/sim/sim.c +++ b/drivers/gpu/nvgpu/common/sim/sim.c @@ -301,40 +301,3 @@ int nvgpu_init_sim_support(struct gk20a *g) g->sim->esc_readl = nvgpu_sim_esc_readl; return 0; } - -#if defined(CONFIG_NVGPU_HAL_NON_FUSA) -static void nvgpu_next_sim_esc_readl(struct gk20a *g, - const char *path, u32 index, u32 *data) -{ - int err; - u32 data_offset; - - sim_write_hdr(g, sim_msg_function_sim_escape_read_v(), - sim_escape_read_hdr_size()); - *sim_msg_param(g, 0) = index; - *sim_msg_param(g, 4) = sizeof(u32); - data_offset = round_up( - nvgpu_safe_add_u64(strlen(path), 1ULL), sizeof(u32)); - *sim_msg_param(g, 8) = data_offset; - strcpy((char *)sim_msg_param(g, sim_escape_read_hdr_size()), path); - - err = issue_rpc_and_wait(g); - - if (err == 0) { - nvgpu_memcpy((u8 *)data, (u8 *)sim_msg_param(g, - nvgpu_safe_add_u32(data_offset, - sim_escape_read_hdr_size())), - sizeof(u32)); - } else { - *data = 0xffffffff; - WARN(1, "issue_rpc_and_wait failed err=%d", err); - } -} - -void nvgpu_next_init_sim_support(struct gk20a *g) -{ - if (g->sim) { - g->sim->esc_readl = nvgpu_next_sim_esc_readl; - } -} -#endif diff --git a/drivers/gpu/nvgpu/common/sim/sim_netlist.c b/drivers/gpu/nvgpu/common/sim/sim_netlist.c index 7b86d6022..c425acb74 100644 --- a/drivers/gpu/nvgpu/common/sim/sim_netlist.c +++ b/drivers/gpu/nvgpu/common/sim/sim_netlist.c @@ -70,7 +70,25 @@ int nvgpu_init_sim_netlist_ctx_vars(struct gk20a *g) struct netlist_u32_list *fecs_inst, *fecs_data; struct netlist_u32_list *gpccs_inst, *gpccs_data; u32 regs_base_index; - +#ifdef CONFIG_NVGPU_NON_FUSA + struct netlist_av_list *sw_non_ctx_local_compute_load; + struct netlist_av_list *sw_non_ctx_local_gfx_load; + struct netlist_av_list *sw_non_ctx_global_compute_load; + struct netlist_av_list *sw_non_ctx_global_gfx_load; +#ifdef CONFIG_NVGPU_DEBUGGER + struct netlist_aiv_list *sys_compute_ctxsw_regs; + struct netlist_aiv_list *gpc_compute_ctxsw_regs; + struct netlist_aiv_list *tpc_compute_ctxsw_regs; + struct netlist_aiv_list *ppc_compute_ctxsw_regs; + struct netlist_aiv_list *etpc_compute_ctxsw_regs; + struct netlist_aiv_list *lts_ctxsw_regs; + struct netlist_aiv_list *sys_gfx_ctxsw_regs; + struct netlist_aiv_list *gpc_gfx_ctxsw_regs; + struct netlist_aiv_list *tpc_gfx_ctxsw_regs; + struct netlist_aiv_list *ppc_gfx_ctxsw_regs; + struct netlist_aiv_list *etpc_gfx_ctxsw_regs; +#endif /* CONFIG_NVGPU_DEBUGGER */ +#endif /* CONFIG_NVGPU_NON_FUSA */ nvgpu_log(g, gpu_dbg_fn | gpu_dbg_info, "querying grctx info from chiplib"); @@ -88,6 +106,18 @@ int nvgpu_init_sim_netlist_ctx_vars(struct gk20a *g) sw_non_ctx_load = nvgpu_netlist_get_sw_non_ctx_load_av_list(g); sw_veid_bundle_init = nvgpu_netlist_get_sw_veid_bundle_init_av_list(g); sw_bundle64_init = nvgpu_netlist_get_sw_bundle64_init_av64_list(g); +#ifdef CONFIG_NVGPU_NON_FUSA + sw_non_ctx_local_compute_load = + nvgpu_netlist_get_sw_non_ctx_local_compute_load_av_list(g); + sw_non_ctx_global_compute_load = + nvgpu_netlist_get_sw_non_ctx_global_compute_load_av_list(g); +#ifdef CONFIG_NVGPU_GRAPHICS + sw_non_ctx_local_gfx_load = + nvgpu_netlist_get_sw_non_ctx_local_gfx_load_av_list(g); + sw_non_ctx_global_gfx_load = + nvgpu_netlist_get_sw_non_ctx_global_gfx_load_av_list(g); +#endif /* CONFIG_NVGPU_GRAPHICS */ +#endif /* CONFIG_NVGPU_NON_FUSA */ #ifdef CONFIG_NVGPU_DEBUGGER sys_ctxsw_regs = nvgpu_netlist_get_sys_ctxsw_regs(g); @@ -95,6 +125,13 @@ int nvgpu_init_sim_netlist_ctx_vars(struct gk20a *g) tpc_ctxsw_regs = nvgpu_netlist_get_tpc_ctxsw_regs(g); #ifdef CONFIG_NVGPU_GRAPHICS zcull_gpc_ctxsw_regs = nvgpu_netlist_get_zcull_gpc_ctxsw_regs(g); +#ifdef CONFIG_NVGPU_NON_FUSA + sys_gfx_ctxsw_regs = nvgpu_netlist_get_sys_gfx_ctxsw_regs(g); + gpc_gfx_ctxsw_regs = nvgpu_netlist_get_gpc_gfx_ctxsw_regs(g); + tpc_gfx_ctxsw_regs = nvgpu_netlist_get_tpc_gfx_ctxsw_regs(g); + ppc_gfx_ctxsw_regs = nvgpu_netlist_get_ppc_gfx_ctxsw_regs(g); + etpc_gfx_ctxsw_regs = nvgpu_netlist_get_etpc_gfx_ctxsw_regs(g); +#endif /* CONFIG_NVGPU_NON_FUSA */ #endif pm_sys_ctxsw_regs = nvgpu_netlist_get_pm_sys_ctxsw_regs(g); pm_gpc_ctxsw_regs = nvgpu_netlist_get_pm_gpc_ctxsw_regs(g); @@ -126,7 +163,22 @@ int nvgpu_init_sim_netlist_ctx_vars(struct gk20a *g) nvgpu_netlist_get_perf_gpc_control_ctxsw_regs(g); perf_pma_control_ctxsw_regs = nvgpu_netlist_get_perf_pma_control_ctxsw_regs(g); - +#ifdef CONFIG_NVGPU_NON_FUSA + sys_compute_ctxsw_regs = + nvgpu_netlist_get_sys_compute_ctxsw_regs(g); + gpc_compute_ctxsw_regs = + nvgpu_netlist_get_gpc_compute_ctxsw_regs(g); + tpc_compute_ctxsw_regs = + nvgpu_netlist_get_tpc_compute_ctxsw_regs(g); + ppc_compute_ctxsw_regs = + nvgpu_netlist_get_ppc_compute_ctxsw_regs(g); + etpc_compute_ctxsw_regs = + nvgpu_netlist_get_etpc_compute_ctxsw_regs(g); + /* + * TODO: https://jirasw.nvidia.com/browse/NVGPU-5761 + */ + lts_ctxsw_regs = nvgpu_netlist_get_lts_ctxsw_regs(g); +#endif /* CONFIG_NVGPU_NON_FUSA */ #endif /* CONFIG_NVGPU_DEBUGGER */ fecs_inst = nvgpu_netlist_get_fecs_inst(g); @@ -338,13 +390,286 @@ int nvgpu_init_sim_netlist_ctx_vars(struct gk20a *g) goto fail; } -#if defined(CONFIG_NVGPU_NON_FUSA) - nvgpu_next_init_sim_netlist_ctxsw_regs(g); -#endif +#ifdef CONFIG_NVGPU_NON_FUSA + /* query sizes and counts */ + g->sim->esc_readl(g, "GRCTX_REG_LIST_SYS_COMPUTE_COUNT", 0, + &sys_compute_ctxsw_regs->count); + + if (nvgpu_netlist_alloc_aiv_list(g, sys_compute_ctxsw_regs) == NULL) { + nvgpu_info(g, "sys_compute_ctxsw_regs failed"); + } + + for (i = 0; i < sys_compute_ctxsw_regs->count; i++) { + struct netlist_aiv *l = sys_compute_ctxsw_regs->l; + g->sim->esc_readl(g, "GRCTX_REG_LIST_SYS_COMPUTE:ADDR", + i, &l[i].addr); + g->sim->esc_readl(g, "GRCTX_REG_LIST_SYS_COMPUTE:INDEX", + i, &l[i].index); + g->sim->esc_readl(g, "GRCTX_REG_LIST_SYS_COMPUTE:VALUE", + i, &l[i].value); + } + + /* query sizes and counts */ + g->sim->esc_readl(g, "GRCTX_REG_LIST_GPC_COMPUTE_COUNT", 0, + &gpc_compute_ctxsw_regs->count); + + if (nvgpu_netlist_alloc_aiv_list(g, gpc_compute_ctxsw_regs) == NULL) { + nvgpu_info(g, "gpc_compute_ctxsw_regs failed"); + } + + for (i = 0; i < gpc_compute_ctxsw_regs->count; i++) { + struct netlist_aiv *l = gpc_compute_ctxsw_regs->l; + g->sim->esc_readl(g, "GRCTX_REG_LIST_GPC_COMPUTE:ADDR", + i, &l[i].addr); + g->sim->esc_readl(g, "GRCTX_REG_LIST_GPC_COMPUTE:INDEX", + i, &l[i].index); + g->sim->esc_readl(g, "GRCTX_REG_LIST_GPC_COMPUTE:VALUE", + i, &l[i].value); + } + + /* query sizes and counts */ + g->sim->esc_readl(g, "GRCTX_REG_LIST_TPC_COMPUTE_COUNT", 0, + &tpc_compute_ctxsw_regs->count); + + if (nvgpu_netlist_alloc_aiv_list(g, tpc_compute_ctxsw_regs) == NULL) { + nvgpu_info(g, "tpc_compute_ctxsw_regs failed"); + } + + for (i = 0; i < tpc_compute_ctxsw_regs->count; i++) { + struct netlist_aiv *l = tpc_compute_ctxsw_regs->l; + g->sim->esc_readl(g, "GRCTX_REG_LIST_TPC_COMPUTE:ADDR", + i, &l[i].addr); + g->sim->esc_readl(g, "GRCTX_REG_LIST_TPC_COMPUTE:INDEX", + i, &l[i].index); + g->sim->esc_readl(g, "GRCTX_REG_LIST_TPC_COMPUTE:VALUE", + i, &l[i].value); + } + + /* query sizes and counts */ + g->sim->esc_readl(g, "GRCTX_REG_LIST_PPC_COMPUTE_COUNT", 0, + &ppc_compute_ctxsw_regs->count); + + if (nvgpu_netlist_alloc_aiv_list(g, ppc_compute_ctxsw_regs) == NULL) { + nvgpu_info(g, "ppc_compute_ctxsw_regs failed"); + } + + for (i = 0; i < ppc_compute_ctxsw_regs->count; i++) { + struct netlist_aiv *l = ppc_compute_ctxsw_regs->l; + g->sim->esc_readl(g, "GRCTX_REG_LIST_PPC_COMPUTE:ADDR", + i, &l[i].addr); + g->sim->esc_readl(g, "GRCTX_REG_LIST_PPC_COMPUTE:INDEX", + i, &l[i].index); + g->sim->esc_readl(g, "GRCTX_REG_LIST_PPC_COMPUTE:VALUE", + i, &l[i].value); + } + + /* query sizes and counts */ + g->sim->esc_readl(g, "GRCTX_REG_LIST_ETPC_COMPUTE_COUNT", 0, + &etpc_compute_ctxsw_regs->count); + + if (nvgpu_netlist_alloc_aiv_list(g, etpc_compute_ctxsw_regs) == NULL) { + nvgpu_info(g, "etpc_compute_ctxsw_regs failed"); + } + + for (i = 0; i < etpc_compute_ctxsw_regs->count; i++) { + struct netlist_aiv *l = etpc_compute_ctxsw_regs->l; + g->sim->esc_readl(g, "GRCTX_REG_LIST_ETPC_COMPUTE:ADDR", + i, &l[i].addr); + g->sim->esc_readl(g, "GRCTX_REG_LIST_ETPC_COMPUTE:INDEX", + i, &l[i].index); + g->sim->esc_readl(g, "GRCTX_REG_LIST_ETPC_COMPUTE:VALUE", + i, &l[i].value); + } + + /* query sizes and counts */ + g->sim->esc_readl(g, "GRCTX_REG_LIST_LTS_BC_COUNT", 0, + <s_ctxsw_regs->count); + nvgpu_log_info(g, "total: %d lts registers", lts_ctxsw_regs->count); + + if (nvgpu_netlist_alloc_aiv_list(g, lts_ctxsw_regs) == NULL) { + nvgpu_info(g, "lts_ctxsw_regs failed"); + } + + for (i = 0U; i < lts_ctxsw_regs->count; i++) { + struct netlist_aiv *l = lts_ctxsw_regs->l; + g->sim->esc_readl(g, "GRCTX_REG_LIST_LTS_BC:ADDR", + i, &l[i].addr); + g->sim->esc_readl(g, "GRCTX_REG_LIST_LTS_BC:INDEX", + i, &l[i].index); + g->sim->esc_readl(g, "GRCTX_REG_LIST_LTS_BC:VALUE", + i, &l[i].value); + nvgpu_log_info(g, "entry(%d) a(0x%x) i(%d) v(0x%x)", i, l[i].addr, + l[i].index, l[i].value); + } + + /* query sizes and counts */ + g->sim->esc_readl(g, "GRCTX_REG_LIST_SYS_GRAPHICS_COUNT", 0, + &sys_gfx_ctxsw_regs->count); + + if (nvgpu_netlist_alloc_aiv_list(g, sys_gfx_ctxsw_regs) == NULL) { + nvgpu_info(g, "sys_gfx_ctxsw_regs failed"); + } + + for (i = 0; i < sys_gfx_ctxsw_regs->count; i++) { + struct netlist_aiv *l = sys_gfx_ctxsw_regs->l; + g->sim->esc_readl(g, "GRCTX_REG_LIST_SYS_GRAPHICS:ADDR", + i, &l[i].addr); + g->sim->esc_readl(g, "GRCTX_REG_LIST_SYS_GRAPHICS:INDEX", + i, &l[i].index); + g->sim->esc_readl(g, "GRCTX_REG_LIST_SYS_GRAPHICS:VALUE", + i, &l[i].value); + } + + /* query sizes and counts */ + g->sim->esc_readl(g, "GRCTX_REG_LIST_GPC_GRAPHICS_COUNT", 0, + &gpc_gfx_ctxsw_regs->count); + + if (nvgpu_netlist_alloc_aiv_list(g, gpc_gfx_ctxsw_regs) == NULL) { + nvgpu_info(g, "gpc_gfx_ctxsw_regs failed"); + } + + for (i = 0; i < gpc_gfx_ctxsw_regs->count; i++) { + struct netlist_aiv *l = gpc_gfx_ctxsw_regs->l; + g->sim->esc_readl(g, "GRCTX_REG_LIST_GPC_GRAPHICS:ADDR", + i, &l[i].addr); + g->sim->esc_readl(g, "GRCTX_REG_LIST_GPC_GRAPHICS:INDEX", + i, &l[i].index); + g->sim->esc_readl(g, "GRCTX_REG_LIST_GPC_GRAPHICS:VALUE", + i, &l[i].value); + } + + /* query sizes and counts */ + g->sim->esc_readl(g, "GRCTX_REG_LIST_TPC_GRAPHICS_COUNT", 0, + &tpc_gfx_ctxsw_regs->count); + + if (nvgpu_netlist_alloc_aiv_list(g, tpc_gfx_ctxsw_regs) == NULL) { + nvgpu_info(g, "tpc_gfx_ctxsw_regs failed"); + } + + for (i = 0; i < tpc_gfx_ctxsw_regs->count; i++) { + struct netlist_aiv *l = tpc_gfx_ctxsw_regs->l; + g->sim->esc_readl(g, "GRCTX_REG_LIST_TPC_GRAPHICS:ADDR", + i, &l[i].addr); + g->sim->esc_readl(g, "GRCTX_REG_LIST_TPC_GRAPHICS:INDEX", + i, &l[i].index); + g->sim->esc_readl(g, "GRCTX_REG_LIST_TPC_GRAPHICS:VALUE", + i, &l[i].value); + } + + /* query sizes and counts */ + g->sim->esc_readl(g, "GRCTX_REG_LIST_PPC_GRAPHICS_COUNT", 0, + &ppc_gfx_ctxsw_regs->count); + + if (nvgpu_netlist_alloc_aiv_list(g, ppc_gfx_ctxsw_regs) == NULL) { + nvgpu_info(g, "ppc_gfx_ctxsw_regs failed"); + } + + for (i = 0; i < ppc_gfx_ctxsw_regs->count; i++) { + struct netlist_aiv *l = ppc_gfx_ctxsw_regs->l; + g->sim->esc_readl(g, "GRCTX_REG_LIST_PPC_GRAPHICS:ADDR", + i, &l[i].addr); + g->sim->esc_readl(g, "GRCTX_REG_LIST_PPC_GRAPHICS:INDEX", + i, &l[i].index); + g->sim->esc_readl(g, "GRCTX_REG_LIST_PPC_GRAPHICS:VALUE", + i, &l[i].value); + } + + /* query sizes and counts */ + g->sim->esc_readl(g, "GRCTX_REG_LIST_ETPC_GRAPHICS_COUNT", 0, + &etpc_gfx_ctxsw_regs->count); + + if (nvgpu_netlist_alloc_aiv_list(g, etpc_gfx_ctxsw_regs) == NULL) { + nvgpu_info(g, "etpc_gfx_ctxsw_regs failed"); + } + + for (i = 0; i < etpc_gfx_ctxsw_regs->count; i++) { + struct netlist_aiv *l = etpc_gfx_ctxsw_regs->l; + g->sim->esc_readl(g, "GRCTX_REG_LIST_ETPC_GRAPHICS:ADDR", + i, &l[i].addr); + g->sim->esc_readl(g, "GRCTX_REG_LIST_ETPC_GRAPHICS:INDEX", + i, &l[i].index); + g->sim->esc_readl(g, "GRCTX_REG_LIST_ETPC_GRAPHICS:VALUE", + i, &l[i].value); + } +#endif /* CONFIG_NVGPU_NON_FUSA */ #endif /* CONFIG_NVGPU_DEBUGGER */ -#if defined(CONFIG_NVGPU_NON_FUSA) - nvgpu_next_init_sim_netlist_ctx_vars(g); -#endif + +#ifdef CONFIG_NVGPU_NON_FUSA + /* query sizes and counts */ + g->sim->esc_readl(g, "GRCTX_NONCTXSW_LOCAL_COMPUTE_REG_SIZE", 0, + &sw_non_ctx_local_compute_load->count); + + if (nvgpu_netlist_alloc_av_list(g, sw_non_ctx_local_compute_load) == + NULL) { + nvgpu_info(g, "sw_non_ctx_local_compute_load failed"); + } + + for (i = 0; i < sw_non_ctx_local_compute_load->count; i++) { + struct netlist_av *l = sw_non_ctx_local_compute_load->l; + g->sim->esc_readl(g, "GRCTX_NONCTXSW_LOCAL_COMPUTE_REG:REG", + i, &l[i].addr); + g->sim->esc_readl(g, "GRCTX_NONCTXSW_LOCAL_COMPUTE_REG:VALUE", + i, &l[i].value); + } + +#ifdef CONFIG_NVGPU_GRAPHICS + sw_non_ctx_local_gfx_load = + nvgpu_netlist_get_sw_non_ctx_local_gfx_load_av_list(g); + + /* query sizes and counts */ + g->sim->esc_readl(g, "GRCTX_NONCTXSW_LOCAL_GRAPHICS_REG_SIZE", 0, + &sw_non_ctx_local_gfx_load->count); + + if (nvgpu_netlist_alloc_av_list(g, sw_non_ctx_local_gfx_load) == + NULL) { + nvgpu_info(g, "sw_non_ctx_local_gfx_load failed"); + } + + for (i = 0; i < sw_non_ctx_local_gfx_load->count; i++) { + struct netlist_av *l = sw_non_ctx_local_gfx_load->l; + g->sim->esc_readl(g, "GRCTX_NONCTXSW_LOCAL_GRAPHICS_REG:REG", + i, &l[i].addr); + g->sim->esc_readl(g, "GRCTX_NONCTXSW_LOCAL_GRAPHICS_REG:VALUE", + i, &l[i].value); + } +#endif /* CONFIG_NVGPU_GRAPHICS */ + + /* query sizes and counts */ + g->sim->esc_readl(g, "GRCTX_NONCTXSW_GLOBAL_COMPUTE_REG_SIZE", 0, + &sw_non_ctx_global_compute_load->count); + + if (nvgpu_netlist_alloc_av_list(g, sw_non_ctx_global_compute_load) == + NULL) { + nvgpu_info(g, "sw_non_ctx_global_compute_load failed"); + } + + for (i = 0; i < sw_non_ctx_global_compute_load->count; i++) { + struct netlist_av *l = sw_non_ctx_global_compute_load->l; + g->sim->esc_readl(g, "GRCTX_NONCTXSW_GLOBAL_COMPUTE_REG:REG", + i, &l[i].addr); + g->sim->esc_readl(g, "GRCTX_NONCTXSW_GLOBAL_COMPUTE_REG:VALUE", + i, &l[i].value); + } + +#ifdef CONFIG_NVGPU_GRAPHICS + /* query sizes and counts */ + g->sim->esc_readl(g, "GRCTX_NONCTXSW_GLOBAL_GRAPHICS_REG_SIZE", 0, + &sw_non_ctx_global_gfx_load->count); + + if (nvgpu_netlist_alloc_av_list(g, sw_non_ctx_global_gfx_load) == + NULL) { + nvgpu_info(g, "sw_non_ctx_global_gfx_load failed"); + } + + for (i = 0; i < sw_non_ctx_global_gfx_load->count; i++) { + struct netlist_av *l = sw_non_ctx_global_gfx_load->l; + g->sim->esc_readl(g, "GRCTX_NONCTXSW_GLOBAL_GRAPHICS_REG:REG", + i, &l[i].addr); + g->sim->esc_readl(g, "GRCTX_NONCTXSW_GLOBAL_GRAPHICS_REG:VALUE", + i, &l[i].value); + } +#endif /* CONFIG_NVGPU_GRAPHICS */ +#endif /* CONFIG_NVGPU_NON_FUSA */ for (i = 0; i < nvgpu_netlist_get_fecs_inst_count(g); i++) { g->sim->esc_readl(g, "GRCTX_UCODE_INST_FECS", @@ -754,7 +1079,6 @@ int nvgpu_init_sim_netlist_ctx_vars(struct gk20a *g) "addr:0x%#08x index:0x%08x value:0x%08x", l[i].addr, l[i].index, l[i].value); } - #endif /* CONFIG_NVGPU_DEBUGGER */ g->netlist_valid = true; @@ -777,9 +1101,6 @@ fail: nvgpu_kfree(g, sw_method_init->l); nvgpu_kfree(g, sw_ctx_load->l); nvgpu_kfree(g, sw_non_ctx_load->l); -#if defined(CONFIG_NVGPU_NON_FUSA) - nvgpu_next_init_sim_netlist_ctx_vars_free(g); -#endif nvgpu_kfree(g, sw_veid_bundle_init->l); #ifdef CONFIG_NVGPU_DEBUGGER nvgpu_kfree(g, sys_ctxsw_regs->l); @@ -808,431 +1129,31 @@ fail: nvgpu_kfree(g, perf_fbp_control_ctxsw_regs->l); nvgpu_kfree(g, perf_gpc_control_ctxsw_regs->l); nvgpu_kfree(g, perf_pma_control_ctxsw_regs->l); -#if defined(CONFIG_NVGPU_NON_FUSA) - nvgpu_next_init_sim_netlist_ctxsw_regs_free(g); -#endif #endif /* CONFIG_NVGPU_DEBUGGER */ - - return err; -} - -#if defined(CONFIG_NVGPU_NON_FUSA) -int nvgpu_next_init_sim_netlist_ctx_vars(struct gk20a *g) -{ - u32 i; - struct netlist_av_list *sw_non_ctx_local_compute_load; - struct netlist_av_list *sw_non_ctx_local_gfx_load; - struct netlist_av_list *sw_non_ctx_global_compute_load; - struct netlist_av_list *sw_non_ctx_global_gfx_load; - - sw_non_ctx_local_compute_load = - nvgpu_next_netlist_get_sw_non_ctx_local_compute_load_av_list(g); - - /* query sizes and counts */ - g->sim->esc_readl(g, "GRCTX_NONCTXSW_LOCAL_COMPUTE_REG_SIZE", 0, - &sw_non_ctx_local_compute_load->count); - - if (nvgpu_netlist_alloc_av_list(g, sw_non_ctx_local_compute_load) == - NULL) { - nvgpu_info(g, "sw_non_ctx_local_compute_load failed"); - } - - for (i = 0; i < sw_non_ctx_local_compute_load->count; i++) { - struct netlist_av *l = sw_non_ctx_local_compute_load->l; - g->sim->esc_readl(g, "GRCTX_NONCTXSW_LOCAL_COMPUTE_REG:REG", - i, &l[i].addr); - g->sim->esc_readl(g, "GRCTX_NONCTXSW_LOCAL_COMPUTE_REG:VALUE", - i, &l[i].value); - } - -#ifdef CONFIG_NVGPU_GRAPHICS - sw_non_ctx_local_gfx_load = - nvgpu_next_netlist_get_sw_non_ctx_local_gfx_load_av_list(g); - - /* query sizes and counts */ - g->sim->esc_readl(g, "GRCTX_NONCTXSW_LOCAL_GRAPHICS_REG_SIZE", 0, - &sw_non_ctx_local_gfx_load->count); - - if (nvgpu_netlist_alloc_av_list(g, sw_non_ctx_local_gfx_load) == - NULL) { - nvgpu_info(g, "sw_non_ctx_local_gfx_load failed"); - } - - for (i = 0; i < sw_non_ctx_local_gfx_load->count; i++) { - struct netlist_av *l = sw_non_ctx_local_gfx_load->l; - g->sim->esc_readl(g, "GRCTX_NONCTXSW_LOCAL_GRAPHICS_REG:REG", - i, &l[i].addr); - g->sim->esc_readl(g, "GRCTX_NONCTXSW_LOCAL_GRAPHICS_REG:VALUE", - i, &l[i].value); - } -#endif - - - sw_non_ctx_global_compute_load = - nvgpu_next_netlist_get_sw_non_ctx_global_compute_load_av_list(g); - - /* query sizes and counts */ - g->sim->esc_readl(g, "GRCTX_NONCTXSW_GLOBAL_COMPUTE_REG_SIZE", 0, - &sw_non_ctx_global_compute_load->count); - - if (nvgpu_netlist_alloc_av_list(g, sw_non_ctx_global_compute_load) == - NULL) { - nvgpu_info(g, "sw_non_ctx_global_compute_load failed"); - } - - for (i = 0; i < sw_non_ctx_global_compute_load->count; i++) { - struct netlist_av *l = sw_non_ctx_global_compute_load->l; - g->sim->esc_readl(g, "GRCTX_NONCTXSW_GLOBAL_COMPUTE_REG:REG", - i, &l[i].addr); - g->sim->esc_readl(g, "GRCTX_NONCTXSW_GLOBAL_COMPUTE_REG:VALUE", - i, &l[i].value); - } - -#ifdef CONFIG_NVGPU_GRAPHICS - sw_non_ctx_global_gfx_load = - nvgpu_next_netlist_get_sw_non_ctx_global_gfx_load_av_list(g); - - /* query sizes and counts */ - g->sim->esc_readl(g, "GRCTX_NONCTXSW_GLOBAL_GRAPHICS_REG_SIZE", 0, - &sw_non_ctx_global_gfx_load->count); - - if (nvgpu_netlist_alloc_av_list(g, sw_non_ctx_global_gfx_load) == - NULL) { - nvgpu_info(g, "sw_non_ctx_global_gfx_load failed"); - } - - for (i = 0; i < sw_non_ctx_global_gfx_load->count; i++) { - struct netlist_av *l = sw_non_ctx_global_gfx_load->l; - g->sim->esc_readl(g, "GRCTX_NONCTXSW_GLOBAL_GRAPHICS_REG:REG", - i, &l[i].addr); - g->sim->esc_readl(g, "GRCTX_NONCTXSW_GLOBAL_GRAPHICS_REG:VALUE", - i, &l[i].value); - } -#endif - return 0; -} - -void nvgpu_next_init_sim_netlist_ctx_vars_free(struct gk20a *g) -{ - struct netlist_av_list *sw_non_ctx_local_compute_load; - struct netlist_av_list *sw_non_ctx_local_gfx_load; - struct netlist_av_list *sw_non_ctx_global_compute_load; - struct netlist_av_list *sw_non_ctx_global_gfx_load; - - sw_non_ctx_local_compute_load = - nvgpu_next_netlist_get_sw_non_ctx_local_compute_load_av_list(g); - sw_non_ctx_global_compute_load = - nvgpu_next_netlist_get_sw_non_ctx_global_compute_load_av_list(g); - - +#ifdef CONFIG_NVGPU_NON_FUSA nvgpu_kfree(g, sw_non_ctx_local_compute_load->l); nvgpu_kfree(g, sw_non_ctx_global_compute_load->l); - #ifdef CONFIG_NVGPU_GRAPHICS - sw_non_ctx_local_gfx_load = - nvgpu_next_netlist_get_sw_non_ctx_local_gfx_load_av_list(g); - sw_non_ctx_global_gfx_load = - nvgpu_next_netlist_get_sw_non_ctx_global_gfx_load_av_list(g); - nvgpu_kfree(g, sw_non_ctx_local_gfx_load->l); nvgpu_kfree(g, sw_non_ctx_global_gfx_load->l); -#endif -} - +#endif /* CONFIG_NVGPU_GRAPHICS */ #ifdef CONFIG_NVGPU_DEBUGGER -int nvgpu_next_init_sim_netlist_ctxsw_regs(struct gk20a *g) -{ - u32 i; - struct netlist_aiv_list *sys_compute_ctxsw_regs; - struct netlist_aiv_list *gpc_compute_ctxsw_regs; - struct netlist_aiv_list *tpc_compute_ctxsw_regs; - struct netlist_aiv_list *ppc_compute_ctxsw_regs; - struct netlist_aiv_list *etpc_compute_ctxsw_regs; - struct netlist_aiv_list *lts_ctxsw_regs; - struct netlist_aiv_list *sys_gfx_ctxsw_regs; - struct netlist_aiv_list *gpc_gfx_ctxsw_regs; - struct netlist_aiv_list *tpc_gfx_ctxsw_regs; - struct netlist_aiv_list *ppc_gfx_ctxsw_regs; - struct netlist_aiv_list *etpc_gfx_ctxsw_regs; - - sys_compute_ctxsw_regs = - nvgpu_next_netlist_get_sys_compute_ctxsw_regs(g); - - /* query sizes and counts */ - g->sim->esc_readl(g, "GRCTX_REG_LIST_SYS_COMPUTE_COUNT", 0, - &sys_compute_ctxsw_regs->count); - - if (nvgpu_netlist_alloc_aiv_list(g, sys_compute_ctxsw_regs) == NULL) { - nvgpu_info(g, "sys_compute_ctxsw_regs failed"); - } - - for (i = 0; i < sys_compute_ctxsw_regs->count; i++) { - struct netlist_aiv *l = sys_compute_ctxsw_regs->l; - g->sim->esc_readl(g, "GRCTX_REG_LIST_SYS_COMPUTE:ADDR", - i, &l[i].addr); - g->sim->esc_readl(g, "GRCTX_REG_LIST_SYS_COMPUTE:INDEX", - i, &l[i].index); - g->sim->esc_readl(g, "GRCTX_REG_LIST_SYS_COMPUTE:VALUE", - i, &l[i].value); - } - - gpc_compute_ctxsw_regs = - nvgpu_next_netlist_get_gpc_compute_ctxsw_regs(g); - - /* query sizes and counts */ - g->sim->esc_readl(g, "GRCTX_REG_LIST_GPC_COMPUTE_COUNT", 0, - &gpc_compute_ctxsw_regs->count); - - if (nvgpu_netlist_alloc_aiv_list(g, gpc_compute_ctxsw_regs) == NULL) { - nvgpu_info(g, "gpc_compute_ctxsw_regs failed"); - } - - for (i = 0; i < gpc_compute_ctxsw_regs->count; i++) { - struct netlist_aiv *l = gpc_compute_ctxsw_regs->l; - g->sim->esc_readl(g, "GRCTX_REG_LIST_GPC_COMPUTE:ADDR", - i, &l[i].addr); - g->sim->esc_readl(g, "GRCTX_REG_LIST_GPC_COMPUTE:INDEX", - i, &l[i].index); - g->sim->esc_readl(g, "GRCTX_REG_LIST_GPC_COMPUTE:VALUE", - i, &l[i].value); - } - - tpc_compute_ctxsw_regs = - nvgpu_next_netlist_get_tpc_compute_ctxsw_regs(g); - - /* query sizes and counts */ - g->sim->esc_readl(g, "GRCTX_REG_LIST_TPC_COMPUTE_COUNT", 0, - &tpc_compute_ctxsw_regs->count); - - if (nvgpu_netlist_alloc_aiv_list(g, tpc_compute_ctxsw_regs) == NULL) { - nvgpu_info(g, "tpc_compute_ctxsw_regs failed"); - } - - for (i = 0; i < tpc_compute_ctxsw_regs->count; i++) { - struct netlist_aiv *l = tpc_compute_ctxsw_regs->l; - g->sim->esc_readl(g, "GRCTX_REG_LIST_TPC_COMPUTE:ADDR", - i, &l[i].addr); - g->sim->esc_readl(g, "GRCTX_REG_LIST_TPC_COMPUTE:INDEX", - i, &l[i].index); - g->sim->esc_readl(g, "GRCTX_REG_LIST_TPC_COMPUTE:VALUE", - i, &l[i].value); - } - - ppc_compute_ctxsw_regs = - nvgpu_next_netlist_get_ppc_compute_ctxsw_regs(g); - - /* query sizes and counts */ - g->sim->esc_readl(g, "GRCTX_REG_LIST_PPC_COMPUTE_COUNT", 0, - &ppc_compute_ctxsw_regs->count); - - if (nvgpu_netlist_alloc_aiv_list(g, ppc_compute_ctxsw_regs) == NULL) { - nvgpu_info(g, "ppc_compute_ctxsw_regs failed"); - } - - for (i = 0; i < ppc_compute_ctxsw_regs->count; i++) { - struct netlist_aiv *l = ppc_compute_ctxsw_regs->l; - g->sim->esc_readl(g, "GRCTX_REG_LIST_PPC_COMPUTE:ADDR", - i, &l[i].addr); - g->sim->esc_readl(g, "GRCTX_REG_LIST_PPC_COMPUTE:INDEX", - i, &l[i].index); - g->sim->esc_readl(g, "GRCTX_REG_LIST_PPC_COMPUTE:VALUE", - i, &l[i].value); - } - - etpc_compute_ctxsw_regs = - nvgpu_next_netlist_get_etpc_compute_ctxsw_regs(g); - - /* query sizes and counts */ - g->sim->esc_readl(g, "GRCTX_REG_LIST_ETPC_COMPUTE_COUNT", 0, - &etpc_compute_ctxsw_regs->count); - - if (nvgpu_netlist_alloc_aiv_list(g, etpc_compute_ctxsw_regs) == NULL) { - nvgpu_info(g, "etpc_compute_ctxsw_regs failed"); - } - - for (i = 0; i < etpc_compute_ctxsw_regs->count; i++) { - struct netlist_aiv *l = etpc_compute_ctxsw_regs->l; - g->sim->esc_readl(g, "GRCTX_REG_LIST_ETPC_COMPUTE:ADDR", - i, &l[i].addr); - g->sim->esc_readl(g, "GRCTX_REG_LIST_ETPC_COMPUTE:INDEX", - i, &l[i].index); - g->sim->esc_readl(g, "GRCTX_REG_LIST_ETPC_COMPUTE:VALUE", - i, &l[i].value); - } - - /* - * TODO: https://jirasw.nvidia.com/browse/NVGPU-5761 - */ - lts_ctxsw_regs = nvgpu_next_netlist_get_lts_ctxsw_regs(g); - - /* query sizes and counts */ - g->sim->esc_readl(g, "GRCTX_REG_LIST_LTS_BC_COUNT", 0, - <s_ctxsw_regs->count); - nvgpu_log_info(g, "total: %d lts registers", lts_ctxsw_regs->count); - - if (nvgpu_netlist_alloc_aiv_list(g, lts_ctxsw_regs) == NULL) { - nvgpu_info(g, "lts_ctxsw_regs failed"); - } - - for (i = 0U; i < lts_ctxsw_regs->count; i++) { - struct netlist_aiv *l = lts_ctxsw_regs->l; - g->sim->esc_readl(g, "GRCTX_REG_LIST_LTS_BC:ADDR", - i, &l[i].addr); - g->sim->esc_readl(g, "GRCTX_REG_LIST_LTS_BC:INDEX", - i, &l[i].index); - g->sim->esc_readl(g, "GRCTX_REG_LIST_LTS_BC:VALUE", - i, &l[i].value); - nvgpu_log_info(g, "entry(%d) a(0x%x) i(%d) v(0x%x)", i, l[i].addr, - l[i].index, l[i].value); - } - - sys_gfx_ctxsw_regs = nvgpu_next_netlist_get_sys_gfx_ctxsw_regs(g); - - /* query sizes and counts */ - g->sim->esc_readl(g, "GRCTX_REG_LIST_SYS_GRAPHICS_COUNT", 0, - &sys_gfx_ctxsw_regs->count); - - if (nvgpu_netlist_alloc_aiv_list(g, sys_gfx_ctxsw_regs) == NULL) { - nvgpu_info(g, "sys_gfx_ctxsw_regs failed"); - } - - for (i = 0; i < sys_gfx_ctxsw_regs->count; i++) { - struct netlist_aiv *l = sys_gfx_ctxsw_regs->l; - g->sim->esc_readl(g, "GRCTX_REG_LIST_SYS_GRAPHICS:ADDR", - i, &l[i].addr); - g->sim->esc_readl(g, "GRCTX_REG_LIST_SYS_GRAPHICS:INDEX", - i, &l[i].index); - g->sim->esc_readl(g, "GRCTX_REG_LIST_SYS_GRAPHICS:VALUE", - i, &l[i].value); - } - - gpc_gfx_ctxsw_regs = nvgpu_next_netlist_get_gpc_gfx_ctxsw_regs(g); - - /* query sizes and counts */ - g->sim->esc_readl(g, "GRCTX_REG_LIST_GPC_GRAPHICS_COUNT", 0, - &gpc_gfx_ctxsw_regs->count); - - if (nvgpu_netlist_alloc_aiv_list(g, gpc_gfx_ctxsw_regs) == NULL) { - nvgpu_info(g, "gpc_gfx_ctxsw_regs failed"); - } - - for (i = 0; i < gpc_gfx_ctxsw_regs->count; i++) { - struct netlist_aiv *l = gpc_gfx_ctxsw_regs->l; - g->sim->esc_readl(g, "GRCTX_REG_LIST_GPC_GRAPHICS:ADDR", - i, &l[i].addr); - g->sim->esc_readl(g, "GRCTX_REG_LIST_GPC_GRAPHICS:INDEX", - i, &l[i].index); - g->sim->esc_readl(g, "GRCTX_REG_LIST_GPC_GRAPHICS:VALUE", - i, &l[i].value); - } - - tpc_gfx_ctxsw_regs = nvgpu_next_netlist_get_tpc_gfx_ctxsw_regs(g); - - /* query sizes and counts */ - g->sim->esc_readl(g, "GRCTX_REG_LIST_TPC_GRAPHICS_COUNT", 0, - &tpc_gfx_ctxsw_regs->count); - - if (nvgpu_netlist_alloc_aiv_list(g, tpc_gfx_ctxsw_regs) == NULL) { - nvgpu_info(g, "tpc_gfx_ctxsw_regs failed"); - } - - for (i = 0; i < tpc_gfx_ctxsw_regs->count; i++) { - struct netlist_aiv *l = tpc_gfx_ctxsw_regs->l; - g->sim->esc_readl(g, "GRCTX_REG_LIST_TPC_GRAPHICS:ADDR", - i, &l[i].addr); - g->sim->esc_readl(g, "GRCTX_REG_LIST_TPC_GRAPHICS:INDEX", - i, &l[i].index); - g->sim->esc_readl(g, "GRCTX_REG_LIST_TPC_GRAPHICS:VALUE", - i, &l[i].value); - } - - ppc_gfx_ctxsw_regs = nvgpu_next_netlist_get_ppc_gfx_ctxsw_regs(g); - - /* query sizes and counts */ - g->sim->esc_readl(g, "GRCTX_REG_LIST_PPC_GRAPHICS_COUNT", 0, - &ppc_gfx_ctxsw_regs->count); - - if (nvgpu_netlist_alloc_aiv_list(g, ppc_gfx_ctxsw_regs) == NULL) { - nvgpu_info(g, "ppc_gfx_ctxsw_regs failed"); - } - - for (i = 0; i < ppc_gfx_ctxsw_regs->count; i++) { - struct netlist_aiv *l = ppc_gfx_ctxsw_regs->l; - g->sim->esc_readl(g, "GRCTX_REG_LIST_PPC_GRAPHICS:ADDR", - i, &l[i].addr); - g->sim->esc_readl(g, "GRCTX_REG_LIST_PPC_GRAPHICS:INDEX", - i, &l[i].index); - g->sim->esc_readl(g, "GRCTX_REG_LIST_PPC_GRAPHICS:VALUE", - i, &l[i].value); - } - - etpc_gfx_ctxsw_regs = nvgpu_next_netlist_get_etpc_gfx_ctxsw_regs(g); - - /* query sizes and counts */ - g->sim->esc_readl(g, "GRCTX_REG_LIST_ETPC_GRAPHICS_COUNT", 0, - &etpc_gfx_ctxsw_regs->count); - - if (nvgpu_netlist_alloc_aiv_list(g, etpc_gfx_ctxsw_regs) == NULL) { - nvgpu_info(g, "etpc_gfx_ctxsw_regs failed"); - } - - for (i = 0; i < etpc_gfx_ctxsw_regs->count; i++) { - struct netlist_aiv *l = etpc_gfx_ctxsw_regs->l; - g->sim->esc_readl(g, "GRCTX_REG_LIST_ETPC_GRAPHICS:ADDR", - i, &l[i].addr); - g->sim->esc_readl(g, "GRCTX_REG_LIST_ETPC_GRAPHICS:INDEX", - i, &l[i].index); - g->sim->esc_readl(g, "GRCTX_REG_LIST_ETPC_GRAPHICS:VALUE", - i, &l[i].value); - } - - return 0; -} - -void nvgpu_next_init_sim_netlist_ctxsw_regs_free(struct gk20a *g) -{ - struct netlist_aiv_list *sys_compute_ctxsw_regs; - struct netlist_aiv_list *gpc_compute_ctxsw_regs; - struct netlist_aiv_list *tpc_compute_ctxsw_regs; - struct netlist_aiv_list *ppc_compute_ctxsw_regs; - struct netlist_aiv_list *etpc_compute_ctxsw_regs; - struct netlist_aiv_list *lts_ctxsw_regs; - struct netlist_aiv_list *sys_gfx_ctxsw_regs; - struct netlist_aiv_list *gpc_gfx_ctxsw_regs; - struct netlist_aiv_list *tpc_gfx_ctxsw_regs; - struct netlist_aiv_list *ppc_gfx_ctxsw_regs; - struct netlist_aiv_list *etpc_gfx_ctxsw_regs; - - sys_compute_ctxsw_regs = - nvgpu_next_netlist_get_sys_compute_ctxsw_regs(g); - gpc_compute_ctxsw_regs = - nvgpu_next_netlist_get_gpc_compute_ctxsw_regs(g); - tpc_compute_ctxsw_regs = - nvgpu_next_netlist_get_tpc_compute_ctxsw_regs(g); - ppc_compute_ctxsw_regs = - nvgpu_next_netlist_get_ppc_compute_ctxsw_regs(g); - etpc_compute_ctxsw_regs = - nvgpu_next_netlist_get_etpc_compute_ctxsw_regs(g); - lts_ctxsw_regs = nvgpu_next_netlist_get_lts_ctxsw_regs(g); - nvgpu_kfree(g, sys_compute_ctxsw_regs->l); nvgpu_kfree(g, gpc_compute_ctxsw_regs->l); nvgpu_kfree(g, tpc_compute_ctxsw_regs->l); nvgpu_kfree(g, ppc_compute_ctxsw_regs->l); nvgpu_kfree(g, etpc_compute_ctxsw_regs->l); nvgpu_kfree(g, lts_ctxsw_regs->l); - - sys_gfx_ctxsw_regs = nvgpu_next_netlist_get_sys_gfx_ctxsw_regs(g); - gpc_gfx_ctxsw_regs = nvgpu_next_netlist_get_gpc_gfx_ctxsw_regs(g); - tpc_gfx_ctxsw_regs = nvgpu_next_netlist_get_tpc_gfx_ctxsw_regs(g); - ppc_gfx_ctxsw_regs = nvgpu_next_netlist_get_ppc_gfx_ctxsw_regs(g); - etpc_gfx_ctxsw_regs = nvgpu_next_netlist_get_etpc_gfx_ctxsw_regs(g); - +#ifdef CONFIG_NVGPU_GRAPHICS nvgpu_kfree(g, sys_gfx_ctxsw_regs->l); nvgpu_kfree(g, gpc_gfx_ctxsw_regs->l); nvgpu_kfree(g, tpc_gfx_ctxsw_regs->l); nvgpu_kfree(g, ppc_gfx_ctxsw_regs->l); nvgpu_kfree(g, etpc_gfx_ctxsw_regs->l); -} + +#endif /* CONFIG_NVGPU_GRAPHICS */ #endif /* CONFIG_NVGPU_DEBUGGER */ -#endif +#endif /* CONFIG_NVGPU_NON_FUSA */ + + return err; +} diff --git a/drivers/gpu/nvgpu/hal/fb/fb_ga10b.c b/drivers/gpu/nvgpu/hal/fb/fb_ga10b.c index 54517c828..e0a0c1fed 100644 --- a/drivers/gpu/nvgpu/hal/fb/fb_ga10b.c +++ b/drivers/gpu/nvgpu/hal/fb/fb_ga10b.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2020, NVIDIA CORPORATION. All rights reserved. + * Copyright (c) 2020-2021, NVIDIA CORPORATION. All rights reserved. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), @@ -212,7 +212,7 @@ int ga10b_fb_set_remote_swizid(struct gk20a *g, bool enable) u32 default_remote_swizid = 0U; struct nvgpu_gpu_instance *gpu_instance; u32 pbdma_id_mask; - struct nvgpu_next_pbdma_info pbdma_info; + struct nvgpu_pbdma_info pbdma_info; u32 pbdma_index; for (index = 0U; index < g->mig.num_gpu_instances; index++) { @@ -248,7 +248,7 @@ int ga10b_fb_set_remote_swizid(struct gk20a *g, bool enable) reg_val); g->ops.runlist.get_pbdma_info(g, - gr_dev->next.rl_pri_base, + gr_dev->rl_pri_base, &pbdma_info); for (pbdma_index = 0U; pbdma_index < PBDMA_PER_RUNLIST_SIZE; @@ -297,7 +297,7 @@ int ga10b_fb_set_remote_swizid(struct gk20a *g, bool enable) } g->ops.runlist.get_pbdma_info(g, - lce->next.rl_pri_base, + lce->rl_pri_base, &pbdma_info); for (pbdma_index = 0U; pbdma_index < PBDMA_PER_RUNLIST_SIZE; diff --git a/drivers/gpu/nvgpu/hal/fifo/ctxsw_timeout_ga10b_fusa.c b/drivers/gpu/nvgpu/hal/fifo/ctxsw_timeout_ga10b_fusa.c index d5813de8e..2425ca4c9 100644 --- a/drivers/gpu/nvgpu/hal/fifo/ctxsw_timeout_ga10b_fusa.c +++ b/drivers/gpu/nvgpu/hal/fifo/ctxsw_timeout_ga10b_fusa.c @@ -55,18 +55,18 @@ static void ga10b_fifo_ctxsw_timeout_clear_and_enable(struct gk20a *g, runlist_intr_0_r(), runlist_intr_0_ctxsw_timeout_eng_reset_f(rleng)); - dev = runlist->nvgpu_next.rl_dev_list[rleng]; + dev = runlist->rl_dev_list[rleng]; if (dev == NULL) { continue; } /* enable ctxsw timeout interrupt */ nvgpu_runlist_writel(g, runlist, runlist_engine_ctxsw_timeout_config_r( - dev->next.rleng_id), + dev->rleng_id), timeout); nvgpu_log_info(g, "ctxsw timeout enable " "rleng: %u timeout_config_val: 0x%08x", - dev->next.rleng_id, timeout); + dev->rleng_id, timeout); } } } @@ -247,7 +247,7 @@ void ga10b_fifo_ctxsw_timeout_isr(struct gk20a *g, /* ctxsw timeout not pending for this rleng */ continue; } - dev = runlist->nvgpu_next.rl_dev_list[rleng]; + dev = runlist->rl_dev_list[rleng]; if (dev == NULL) { nvgpu_err(g, "ctxsw timeout for rleng: %u but " "dev is invalid", rleng); @@ -257,10 +257,10 @@ void ga10b_fifo_ctxsw_timeout_isr(struct gk20a *g, /* dump ctxsw timeout for rleng. useful for debugging */ reg_val = nvgpu_runlist_readl(g, runlist, runlist_engine_ctxsw_timeout_config_r( - dev->next.rleng_id)); + dev->rleng_id)); timeout = runlist_engine_ctxsw_timeout_config_period_v(reg_val); nvgpu_log_info(g, "rleng: %u ctxsw timeout period = 0x%x", - dev->next.rleng_id, timeout); + dev->rleng_id, timeout); /* handle ctxsw timeout */ tsgid = ga10b_fifo_ctxsw_timeout_info(g, runlist, rleng, diff --git a/drivers/gpu/nvgpu/hal/fifo/engine_status_ga10b_fusa.c b/drivers/gpu/nvgpu/hal/fifo/engine_status_ga10b_fusa.c index ca531d1e3..a42d62833 100644 --- a/drivers/gpu/nvgpu/hal/fifo/engine_status_ga10b_fusa.c +++ b/drivers/gpu/nvgpu/hal/fifo/engine_status_ga10b_fusa.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2020, NVIDIA CORPORATION. All rights reserved. + * Copyright (c) 2020-2021, NVIDIA CORPORATION. All rights reserved. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), @@ -107,15 +107,15 @@ void ga10b_read_engine_status_info(struct gk20a *g, u32 engine_id, dev = g->fifo.host_engines[engine_id]; engine_reg0_data = nvgpu_readl(g, nvgpu_safe_add_u32( - dev->next.rl_pri_base, - runlist_engine_status0_r(dev->next.rleng_id))); + dev->rl_pri_base, + runlist_engine_status0_r(dev->rleng_id))); engine_reg1_data = nvgpu_readl(g, nvgpu_safe_add_u32( - dev->next.rl_pri_base, - runlist_engine_status1_r(dev->next.rleng_id))); + dev->rl_pri_base, + runlist_engine_status1_r(dev->rleng_id))); status->reg_data = engine_reg0_data; - status->nvgpu_next.reg1_data = engine_reg1_data; + status->reg1_data = engine_reg1_data; /* populate the engine_state enum */ status->is_busy = runlist_engine_status0_engine_v(engine_reg0_data) == diff --git a/drivers/gpu/nvgpu/hal/fifo/engines_gp10b_fusa.c b/drivers/gpu/nvgpu/hal/fifo/engines_gp10b_fusa.c index 56a0590f1..400571a17 100644 --- a/drivers/gpu/nvgpu/hal/fifo/engines_gp10b_fusa.c +++ b/drivers/gpu/nvgpu/hal/fifo/engines_gp10b_fusa.c @@ -65,7 +65,10 @@ int gp10b_engine_init_ce_info(struct nvgpu_fifo *f) #if defined(CONFIG_NVGPU_HAL_NON_FUSA) { - int err = nvgpu_next_engine_init_one_dev(g, dev); + /* + * Fill Ampere+ device fields. + */ + int err = nvgpu_engine_init_one_dev_extra(g, dev); if (err != 0) { return err; } diff --git a/drivers/gpu/nvgpu/hal/fifo/fifo_intr_ga10b_fusa.c b/drivers/gpu/nvgpu/hal/fifo/fifo_intr_ga10b_fusa.c index 47a9f1201..b92c1c864 100644 --- a/drivers/gpu/nvgpu/hal/fifo/fifo_intr_ga10b_fusa.c +++ b/drivers/gpu/nvgpu/hal/fifo/fifo_intr_ga10b_fusa.c @@ -452,14 +452,14 @@ void ga10b_fifo_intr_unset_recover_mask(struct gk20a *g) void ga10b_fifo_pbdma_isr(struct gk20a *g, struct nvgpu_runlist *runlist, u32 pbdma_idx) { u32 pbdma_id; - const struct nvgpu_next_pbdma_info *pbdma_info; + const struct nvgpu_pbdma_info *pbdma_info; if (pbdma_idx >= PBDMA_PER_RUNLIST_SIZE) { nvgpu_err(g, "pbdma_idx(%d) >= max_pbdmas_per_runlist(%d)", pbdma_idx, PBDMA_PER_RUNLIST_SIZE); return; } - pbdma_info = runlist->nvgpu_next.pbdma_info; + pbdma_info = runlist->pbdma_info; pbdma_id = pbdma_info->pbdma_id[pbdma_idx]; if (pbdma_id == PBDMA_ID_INVALID) { nvgpu_err(g, "runlist_id(%d), pbdma_idx(%d): invalid PBDMA", diff --git a/drivers/gpu/nvgpu/hal/fifo/fifo_utils_ga10b_fusa.c b/drivers/gpu/nvgpu/hal/fifo/fifo_utils_ga10b_fusa.c index 8ab37ae2c..5ff0255e1 100644 --- a/drivers/gpu/nvgpu/hal/fifo/fifo_utils_ga10b_fusa.c +++ b/drivers/gpu/nvgpu/hal/fifo/fifo_utils_ga10b_fusa.c @@ -34,7 +34,7 @@ u32 nvgpu_runlist_readl(struct gk20a *g, struct nvgpu_runlist *runlist, u32 runlist_pri_base = 0U; nvgpu_assert(runlist != NULL); - runlist_pri_base = runlist->nvgpu_next.runlist_pri_base; + runlist_pri_base = runlist->runlist_pri_base; nvgpu_assert(runlist_pri_base != 0U); return nvgpu_readl(g, nvgpu_safe_add_u32(runlist_pri_base, r)); @@ -46,7 +46,7 @@ void nvgpu_runlist_writel(struct gk20a *g, struct nvgpu_runlist *runlist, u32 runlist_pri_base = 0U; nvgpu_assert(runlist != NULL); - runlist_pri_base = runlist->nvgpu_next.runlist_pri_base; + runlist_pri_base = runlist->runlist_pri_base; nvgpu_assert(runlist_pri_base != 0U); nvgpu_writel(g, nvgpu_safe_add_u32(runlist_pri_base, r), v); @@ -58,7 +58,7 @@ u32 nvgpu_chram_bar0_readl(struct gk20a *g, struct nvgpu_runlist *runlist, u32 chram_bar0_offset = 0U; nvgpu_assert(runlist != NULL); - chram_bar0_offset = runlist->nvgpu_next.chram_bar0_offset; + chram_bar0_offset = runlist->chram_bar0_offset; nvgpu_assert(chram_bar0_offset != 0U); return nvgpu_readl(g, nvgpu_safe_add_u32(chram_bar0_offset, r)); @@ -70,7 +70,7 @@ void nvgpu_chram_bar0_writel(struct gk20a *g, u32 chram_bar0_offset = 0U; nvgpu_assert(runlist != NULL); - chram_bar0_offset = runlist->nvgpu_next.chram_bar0_offset; + chram_bar0_offset = runlist->chram_bar0_offset; nvgpu_assert(chram_bar0_offset != 0U); nvgpu_writel(g, nvgpu_safe_add_u32(chram_bar0_offset, r), v); diff --git a/drivers/gpu/nvgpu/hal/fifo/pbdma_ga100_fusa.c b/drivers/gpu/nvgpu/hal/fifo/pbdma_ga100_fusa.c index 9b9f39a11..6034df77a 100644 --- a/drivers/gpu/nvgpu/hal/fifo/pbdma_ga100_fusa.c +++ b/drivers/gpu/nvgpu/hal/fifo/pbdma_ga100_fusa.c @@ -57,7 +57,7 @@ u32 ga100_pbdma_set_clear_intr_offsets(struct gk20a *g, u32 ga100_pbdma_get_fc_target(const struct nvgpu_device *dev) { - return (pbdma_target_engine_f(dev->next.rleng_id) | + return (pbdma_target_engine_f(dev->rleng_id) | pbdma_target_eng_ctx_valid_true_f() | pbdma_target_ce_ctx_valid_true_f()); } @@ -68,9 +68,9 @@ static void ga100_pbdma_force_ce_split_set(struct gk20a *g, u32 reg; u32 i; u32 pbdma_id; - const struct nvgpu_next_pbdma_info *pbdma_info = NULL; + const struct nvgpu_pbdma_info *pbdma_info = NULL; - pbdma_info = runlist->nvgpu_next.pbdma_info; + pbdma_info = runlist->pbdma_info; for (i = 0U; i < PBDMA_PER_RUNLIST_SIZE; i++) { pbdma_id = pbdma_info->pbdma_id[i]; if (pbdma_id == U32_MAX) { diff --git a/drivers/gpu/nvgpu/hal/fifo/pbdma_ga10b_fusa.c b/drivers/gpu/nvgpu/hal/fifo/pbdma_ga10b_fusa.c index 86399dda4..2cb6d6b8b 100644 --- a/drivers/gpu/nvgpu/hal/fifo/pbdma_ga10b_fusa.c +++ b/drivers/gpu/nvgpu/hal/fifo/pbdma_ga10b_fusa.c @@ -597,7 +597,7 @@ u32 ga10b_pbdma_set_intr_notify(u32 eng_intr_vector) u32 ga10b_pbdma_get_fc_target(const struct nvgpu_device *dev) { - return (pbdma_target_engine_f(dev->next.rleng_id) | + return (pbdma_target_engine_f(dev->rleng_id) | pbdma_target_eng_ctx_valid_true_f() | pbdma_target_ce_ctx_valid_true_f()); } diff --git a/drivers/gpu/nvgpu/hal/fifo/runlist_ga10b.h b/drivers/gpu/nvgpu/hal/fifo/runlist_ga10b.h index 0e8a73e8f..1a4d04381 100644 --- a/drivers/gpu/nvgpu/hal/fifo/runlist_ga10b.h +++ b/drivers/gpu/nvgpu/hal/fifo/runlist_ga10b.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2020, NVIDIA CORPORATION. All rights reserved. + * Copyright (c) 2020-2021, NVIDIA CORPORATION. All rights reserved. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), @@ -26,14 +26,14 @@ #include struct gk20a; -struct nvgpu_next_pbdma_info; +struct nvgpu_pbdma_info; u32 ga10b_runlist_get_runlist_id(struct gk20a *g, u32 runlist_pri_base); u32 ga10b_runlist_get_engine_id_from_rleng_id(struct gk20a *g, u32 rleng_id, u32 runlist_pri_base); u32 ga10b_runlist_get_chram_bar0_offset(struct gk20a *g, u32 runlist_pri_base); void ga10b_runlist_get_pbdma_info(struct gk20a *g, u32 runlist_pri_base, - struct nvgpu_next_pbdma_info *pbdma_info); + struct nvgpu_pbdma_info *pbdma_info); u32 ga10b_runlist_get_engine_intr_id(struct gk20a *g, u32 runlist_pri_base, u32 rleng_id); u32 ga10b_runlist_get_esched_fb_thread_id(struct gk20a *g, u32 runlist_pri_base); diff --git a/drivers/gpu/nvgpu/hal/fifo/runlist_ga10b_fusa.c b/drivers/gpu/nvgpu/hal/fifo/runlist_ga10b_fusa.c index 251bbb7cc..0048d504d 100644 --- a/drivers/gpu/nvgpu/hal/fifo/runlist_ga10b_fusa.c +++ b/drivers/gpu/nvgpu/hal/fifo/runlist_ga10b_fusa.c @@ -66,7 +66,7 @@ u32 ga10b_runlist_get_chram_bar0_offset(struct gk20a *g, u32 runlist_pri_base) * is not populated. */ void ga10b_runlist_get_pbdma_info(struct gk20a *g, u32 runlist_pri_base, - struct nvgpu_next_pbdma_info *pbdma_info) + struct nvgpu_pbdma_info *pbdma_info) { u32 i, pbdma_config; diff --git a/drivers/gpu/nvgpu/hal/gr/gr/gr_ga100.c b/drivers/gpu/nvgpu/hal/gr/gr/gr_ga100.c index 89528fc2f..e736e3b79 100644 --- a/drivers/gpu/nvgpu/hal/gr/gr/gr_ga100.c +++ b/drivers/gpu/nvgpu/hal/gr/gr/gr_ga100.c @@ -397,7 +397,7 @@ int gr_ga100_process_context_buffer_priv_segment(struct gk20a *g, /* Process the SYS/BE segment. */ if ((addr_type == CTXSW_ADDR_TYPE_SYS) || (addr_type == CTXSW_ADDR_TYPE_ROP)) { - list = nvgpu_next_netlist_get_sys_compute_ctxsw_regs(g); + list = nvgpu_netlist_get_sys_compute_ctxsw_regs(g); for (i = 0; i < list->count; i++) { reg = &list->l[i]; address = reg->addr; @@ -409,7 +409,7 @@ int gr_ga100_process_context_buffer_priv_segment(struct gk20a *g, } } #ifdef CONFIG_NVGPU_GRAPHICS - list = nvgpu_next_netlist_get_sys_gfx_ctxsw_regs(g); + list = nvgpu_netlist_get_sys_gfx_ctxsw_regs(g); for (i = 0; i < list->count; i++) { reg = &list->l[i]; address = reg->addr; @@ -417,7 +417,7 @@ int gr_ga100_process_context_buffer_priv_segment(struct gk20a *g, if (pri_addr == address) { *priv_offset = sys_offset + - nvgpu_next_netlist_get_sys_compute_ctxsw_regs(g)->count * 4U; + nvgpu_netlist_get_sys_compute_ctxsw_regs(g)->count * 4U; return 0; } } @@ -432,9 +432,9 @@ int gr_ga100_process_context_buffer_priv_segment(struct gk20a *g, * count represents an entry of 4 bytes. */ if (addr_type == CTXSW_ADDR_TYPE_LTS_MAIN) { - sys_offset = nvgpu_next_netlist_get_sys_ctxsw_regs_count(g); + sys_offset = nvgpu_netlist_get_sys_ctxsw_regs_count(g); sys_offset <<= 2; - list = nvgpu_next_netlist_get_lts_ctxsw_regs(g); + list = nvgpu_netlist_get_lts_ctxsw_regs(g); for (i = 0; i < list->count; i++) { reg = &list->l[i]; address = reg->addr; @@ -450,7 +450,7 @@ int gr_ga100_process_context_buffer_priv_segment(struct gk20a *g, /* Process the TPC segment. */ if (addr_type == CTXSW_ADDR_TYPE_TPC) { for (tpc_num = 0; tpc_num < num_tpcs; tpc_num++) { - list = nvgpu_next_netlist_get_tpc_compute_ctxsw_regs(g); + list = nvgpu_netlist_get_tpc_compute_ctxsw_regs(g); for (i = 0; i < list->count; i++) { reg = &list->l[i]; address = reg->addr; @@ -474,7 +474,7 @@ int gr_ga100_process_context_buffer_priv_segment(struct gk20a *g, } } #ifdef CONFIG_NVGPU_GRAPHICS - list = nvgpu_next_netlist_get_tpc_gfx_ctxsw_regs(g); + list = nvgpu_netlist_get_tpc_gfx_ctxsw_regs(g); for (i = 0; i < list->count; i++) { reg = &list->l[i]; address = reg->addr; @@ -494,7 +494,7 @@ int gr_ga100_process_context_buffer_priv_segment(struct gk20a *g, if (pri_addr == address) { *priv_offset = tpc_offset + - nvgpu_next_netlist_get_tpc_compute_ctxsw_regs(g)->count * num_tpcs * 4U; + nvgpu_netlist_get_tpc_compute_ctxsw_regs(g)->count * num_tpcs * 4U; return 0; } } @@ -507,7 +507,7 @@ int gr_ga100_process_context_buffer_priv_segment(struct gk20a *g, } for (tpc_num = 0; tpc_num < num_tpcs; tpc_num++) { - list = nvgpu_next_netlist_get_etpc_compute_ctxsw_regs(g); + list = nvgpu_netlist_get_etpc_compute_ctxsw_regs(g); for (i = 0; i < list->count; i++) { reg = &list->l[i]; address = reg->addr; @@ -535,7 +535,7 @@ int gr_ga100_process_context_buffer_priv_segment(struct gk20a *g, } } #ifdef CONFIG_NVGPU_GRAPHICS - list = nvgpu_next_netlist_get_etpc_gfx_ctxsw_regs(g); + list = nvgpu_netlist_get_etpc_gfx_ctxsw_regs(g); for (i = 0; i < list->count; i++) { reg = &list->l[i]; address = reg->addr; @@ -555,7 +555,7 @@ int gr_ga100_process_context_buffer_priv_segment(struct gk20a *g, if (pri_addr == address) { *priv_offset = tpc_offset + - nvgpu_next_netlist_get_etpc_compute_ctxsw_regs(g)->count * num_tpcs * 4U; + nvgpu_netlist_get_etpc_compute_ctxsw_regs(g)->count * num_tpcs * 4U; nvgpu_log(g, gpu_dbg_fn | gpu_dbg_gpu_dbg, "egpc/etpc gfx priv_offset=0x%#08x", @@ -571,7 +571,7 @@ int gr_ga100_process_context_buffer_priv_segment(struct gk20a *g, /* Process the PPC segment. */ if (addr_type == CTXSW_ADDR_TYPE_PPC) { for (ppc_num = 0; ppc_num < num_ppcs; ppc_num++) { - list = nvgpu_next_netlist_get_ppc_compute_ctxsw_regs(g); + list = nvgpu_netlist_get_ppc_compute_ctxsw_regs(g); for (i = 0; i < list->count; i++) { reg = &list->l[i]; address = reg->addr; @@ -595,7 +595,7 @@ int gr_ga100_process_context_buffer_priv_segment(struct gk20a *g, } } #ifdef CONFIG_NVGPU_GRAPHICS - list = nvgpu_next_netlist_get_ppc_gfx_ctxsw_regs(g); + list = nvgpu_netlist_get_ppc_gfx_ctxsw_regs(g); for (i = 0; i < list->count; i++) { reg = &list->l[i]; address = reg->addr; @@ -615,7 +615,7 @@ int gr_ga100_process_context_buffer_priv_segment(struct gk20a *g, if (pri_addr == address) { *priv_offset = ppc_offset + - nvgpu_next_netlist_get_ppc_compute_ctxsw_regs(g)->count * num_ppcs * 4U; + nvgpu_netlist_get_ppc_compute_ctxsw_regs(g)->count * num_ppcs * 4U; return 0; } } @@ -625,7 +625,7 @@ int gr_ga100_process_context_buffer_priv_segment(struct gk20a *g, /* Process the GPC segment. */ if (addr_type == CTXSW_ADDR_TYPE_GPC) { - list = nvgpu_next_netlist_get_gpc_compute_ctxsw_regs(g); + list = nvgpu_netlist_get_gpc_compute_ctxsw_regs(g); for (i = 0; i < list->count; i++) { reg = &list->l[i]; @@ -642,7 +642,7 @@ int gr_ga100_process_context_buffer_priv_segment(struct gk20a *g, } } #ifdef CONFIG_NVGPU_GRAPHICS - list = nvgpu_next_netlist_get_gpc_gfx_ctxsw_regs(g); + list = nvgpu_netlist_get_gpc_gfx_ctxsw_regs(g); for (i = 0; i < list->count; i++) { reg = &list->l[i]; @@ -655,7 +655,7 @@ int gr_ga100_process_context_buffer_priv_segment(struct gk20a *g, if (pri_addr == address) { *priv_offset = gpc_offset + - nvgpu_next_netlist_get_gpc_compute_ctxsw_regs(g)->count * 4U; + nvgpu_netlist_get_gpc_compute_ctxsw_regs(g)->count * 4U; return 0; } } diff --git a/drivers/gpu/nvgpu/hal/gr/gr/gr_ga10b.c b/drivers/gpu/nvgpu/hal/gr/gr/gr_ga10b.c index 06d07313e..89e604a1f 100644 --- a/drivers/gpu/nvgpu/hal/gr/gr/gr_ga10b.c +++ b/drivers/gpu/nvgpu/hal/gr/gr/gr_ga10b.c @@ -622,7 +622,7 @@ int gr_ga10b_process_context_buffer_priv_segment(struct gk20a *g, /* Process the SYS/BE segment. */ if ((addr_type == CTXSW_ADDR_TYPE_SYS) || (addr_type == CTXSW_ADDR_TYPE_ROP)) { - list = nvgpu_next_netlist_get_sys_compute_ctxsw_regs(g); + list = nvgpu_netlist_get_sys_compute_ctxsw_regs(g); for (i = 0; i < list->count; i++) { reg = &list->l[i]; address = reg->addr; @@ -634,7 +634,7 @@ int gr_ga10b_process_context_buffer_priv_segment(struct gk20a *g, } } #ifdef CONFIG_NVGPU_GRAPHICS - list = nvgpu_next_netlist_get_sys_gfx_ctxsw_regs(g); + list = nvgpu_netlist_get_sys_gfx_ctxsw_regs(g); for (i = 0; i < list->count; i++) { reg = &list->l[i]; address = reg->addr; @@ -652,7 +652,7 @@ int gr_ga10b_process_context_buffer_priv_segment(struct gk20a *g, * Process the LTS segment. */ if (addr_type == CTXSW_ADDR_TYPE_LTS_MAIN) { - list = nvgpu_next_netlist_get_lts_ctxsw_regs(g); + list = nvgpu_netlist_get_lts_ctxsw_regs(g); for (i = 0; i < list->count; i++) { reg = &list->l[i]; address = reg->addr; @@ -668,7 +668,7 @@ int gr_ga10b_process_context_buffer_priv_segment(struct gk20a *g, /* Process the TPC segment. */ if (addr_type == CTXSW_ADDR_TYPE_TPC) { for (tpc_num = 0; tpc_num < num_tpcs; tpc_num++) { - list = nvgpu_next_netlist_get_tpc_compute_ctxsw_regs(g); + list = nvgpu_netlist_get_tpc_compute_ctxsw_regs(g); for (i = 0; i < list->count; i++) { reg = &list->l[i]; address = reg->addr; @@ -686,7 +686,7 @@ int gr_ga10b_process_context_buffer_priv_segment(struct gk20a *g, } } #ifdef CONFIG_NVGPU_GRAPHICS - list = nvgpu_next_netlist_get_tpc_gfx_ctxsw_regs(g); + list = nvgpu_netlist_get_tpc_gfx_ctxsw_regs(g); for (i = 0; i < list->count; i++) { reg = &list->l[i]; address = reg->addr; @@ -712,7 +712,7 @@ int gr_ga10b_process_context_buffer_priv_segment(struct gk20a *g, } for (tpc_num = 0; tpc_num < num_tpcs; tpc_num++) { - list = nvgpu_next_netlist_get_etpc_compute_ctxsw_regs(g); + list = nvgpu_netlist_get_etpc_compute_ctxsw_regs(g); for (i = 0; i < list->count; i++) { reg = &list->l[i]; address = reg->addr; @@ -740,7 +740,7 @@ int gr_ga10b_process_context_buffer_priv_segment(struct gk20a *g, } } #ifdef CONFIG_NVGPU_GRAPHICS - list = nvgpu_next_netlist_get_etpc_gfx_ctxsw_regs(g); + list = nvgpu_netlist_get_etpc_gfx_ctxsw_regs(g); for (i = 0; i < list->count; i++) { reg = &list->l[i]; address = reg->addr; @@ -775,7 +775,7 @@ int gr_ga10b_process_context_buffer_priv_segment(struct gk20a *g, /* Process the PPC segment. */ if (addr_type == CTXSW_ADDR_TYPE_PPC) { for (ppc_num = 0; ppc_num < num_ppcs; ppc_num++) { - list = nvgpu_next_netlist_get_ppc_compute_ctxsw_regs(g); + list = nvgpu_netlist_get_ppc_compute_ctxsw_regs(g); for (i = 0; i < list->count; i++) { reg = &list->l[i]; address = reg->addr; @@ -799,7 +799,7 @@ int gr_ga10b_process_context_buffer_priv_segment(struct gk20a *g, } } #ifdef CONFIG_NVGPU_GRAPHICS - list = nvgpu_next_netlist_get_ppc_gfx_ctxsw_regs(g); + list = nvgpu_netlist_get_ppc_gfx_ctxsw_regs(g); for (i = 0; i < list->count; i++) { reg = &list->l[i]; address = reg->addr; @@ -828,7 +828,7 @@ int gr_ga10b_process_context_buffer_priv_segment(struct gk20a *g, /* Process the GPC segment. */ if (addr_type == CTXSW_ADDR_TYPE_GPC) { - list = nvgpu_next_netlist_get_gpc_compute_ctxsw_regs(g); + list = nvgpu_netlist_get_gpc_compute_ctxsw_regs(g); for (i = 0; i < list->count; i++) { reg = &list->l[i]; @@ -845,7 +845,7 @@ int gr_ga10b_process_context_buffer_priv_segment(struct gk20a *g, } } #ifdef CONFIG_NVGPU_GRAPHICS - list = nvgpu_next_netlist_get_gpc_gfx_ctxsw_regs(g); + list = nvgpu_netlist_get_gpc_gfx_ctxsw_regs(g); for (i = 0; i < list->count; i++) { reg = &list->l[i]; diff --git a/drivers/gpu/nvgpu/hal/grmgr/grmgr_ga10b.c b/drivers/gpu/nvgpu/hal/grmgr/grmgr_ga10b.c index 5c78018c1..4736b2221 100644 --- a/drivers/gpu/nvgpu/hal/grmgr/grmgr_ga10b.c +++ b/drivers/gpu/nvgpu/hal/grmgr/grmgr_ga10b.c @@ -166,10 +166,10 @@ static bool ga10b_grmgr_is_syspipe_lce(struct gk20a *g, u32 lce_fb_thread_id; gr_fb_thread_id = g->ops.runlist.get_esched_fb_thread_id(g, - gr_dev->next.rl_pri_base); + gr_dev->rl_pri_base); lce_fb_thread_id = g->ops.runlist.get_esched_fb_thread_id(g, - lce_dev->next.rl_pri_base); + lce_dev->rl_pri_base); nvgpu_log(g, gpu_dbg_mig, "gr_engine_id[%u] lce_engine_id[%u] " diff --git a/drivers/gpu/nvgpu/hal/init/hal_ga100.c b/drivers/gpu/nvgpu/hal/init/hal_ga100.c index 13e1185ad..005a4bca9 100644 --- a/drivers/gpu/nvgpu/hal/init/hal_ga100.c +++ b/drivers/gpu/nvgpu/hal/init/hal_ga100.c @@ -1118,7 +1118,7 @@ static const struct gops_runlist ga100_ops_runlist = { .get_chram_bar0_offset = ga10b_runlist_get_chram_bar0_offset, .get_pbdma_info = ga10b_runlist_get_pbdma_info, .get_engine_intr_id = ga10b_runlist_get_engine_intr_id, - .init_enginfo = nvgpu_next_runlist_init_enginfo, + .init_enginfo = nvgpu_runlist_init_enginfo, .get_tsg_max_timeslice = gv11b_runlist_max_timeslice, .get_esched_fb_thread_id = ga10b_runlist_get_esched_fb_thread_id, }; diff --git a/drivers/gpu/nvgpu/hal/init/hal_ga10b.c b/drivers/gpu/nvgpu/hal/init/hal_ga10b.c index 2fcdcd26b..0a55a65d2 100644 --- a/drivers/gpu/nvgpu/hal/init/hal_ga10b.c +++ b/drivers/gpu/nvgpu/hal/init/hal_ga10b.c @@ -268,6 +268,7 @@ #include #ifdef CONFIG_NVGPU_SIM #include +#include "hal/sim/sim_ga10b.h" #endif #include "hal/grmgr/grmgr_ga10b.h" @@ -1106,7 +1107,7 @@ static const struct gops_runlist ga10b_ops_runlist = { .get_chram_bar0_offset = ga10b_runlist_get_chram_bar0_offset, .get_pbdma_info = ga10b_runlist_get_pbdma_info, .get_engine_intr_id = ga10b_runlist_get_engine_intr_id, - .init_enginfo = nvgpu_next_runlist_init_enginfo, + .init_enginfo = nvgpu_runlist_init_enginfo, .get_tsg_max_timeslice = gv11b_runlist_max_timeslice, .get_esched_fb_thread_id = ga10b_runlist_get_esched_fb_thread_id, }; @@ -1861,8 +1862,8 @@ int ga10b_init_hal(struct gk20a *g) #endif #ifdef CONFIG_NVGPU_SIM - /* SIM specific overrides */ - nvgpu_next_init_sim_support(g); + /* SIM specific overrides for ga10b */ + nvgpu_init_sim_support_ga10b(g); if (nvgpu_is_enabled(g, NVGPU_IS_FMODEL)){ /* Disable fb mem_unlock */ gops->fb.mem_unlock = NULL; diff --git a/drivers/gpu/nvgpu/hal/mc/mc_intr_ga10b_fusa.c b/drivers/gpu/nvgpu/hal/mc/mc_intr_ga10b_fusa.c index 610da88b5..0eceb6b46 100644 --- a/drivers/gpu/nvgpu/hal/mc/mc_intr_ga10b_fusa.c +++ b/drivers/gpu/nvgpu/hal/mc/mc_intr_ga10b_fusa.c @@ -44,7 +44,7 @@ static bool ga10b_intr_is_unit_pending(struct gk20a *g, u32 intr_unit_pending = false; struct nvgpu_intr_unit_info *intr_unit_info; - intr_unit_info = g->mc.nvgpu_next.intr_unit_info; + intr_unit_info = g->mc.intr_unit_info; subtree_mask = intr_unit_info[intr_unit].subtree_mask; subtree_mask_lo = u64_lo32(subtree_mask); @@ -167,15 +167,15 @@ static void ga10b_intr_config(struct gk20a *g, bool enable, u32 subtree, u64 subtree_mask) { if (enable) { - g->mc.nvgpu_next.subtree_mask_restore[subtree] |= + g->mc.subtree_mask_restore[subtree] |= subtree_mask; - subtree_mask = g->mc.nvgpu_next.subtree_mask_restore[subtree]; + subtree_mask = g->mc.subtree_mask_restore[subtree]; ga10b_intr_subtree_enable(g, subtree, subtree_mask); } else { - g->mc.nvgpu_next.subtree_mask_restore[subtree] &= + g->mc.subtree_mask_restore[subtree] &= ~(subtree_mask); - subtree_mask = g->mc.nvgpu_next.subtree_mask_restore[subtree]; + subtree_mask = g->mc.subtree_mask_restore[subtree]; ga10b_intr_subtree_disable(g, subtree, subtree_mask); } @@ -331,7 +331,7 @@ bool ga10b_mc_intr_get_unit_info(struct gk20a *g, u32 unit) struct nvgpu_intr_unit_info *intr_unit_info; u64 tmp_subtree_mask = 0ULL; - intr_unit_info = &g->mc.nvgpu_next.intr_unit_info[unit]; + intr_unit_info = &g->mc.intr_unit_info[unit]; switch (unit) { case NVGPU_CIC_INTR_UNIT_BUS: @@ -710,7 +710,7 @@ static void ga10b_intr_gr_stall_interrupt_handling(struct gk20a *g, u32 gr_instance_id; const struct nvgpu_device *dev; struct nvgpu_intr_unit_info *intr_unit_info = - &g->mc.nvgpu_next.intr_unit_info[NVGPU_CIC_INTR_UNIT_GR_STALL]; + &g->mc.intr_unit_info[NVGPU_CIC_INTR_UNIT_GR_STALL]; vectorid = intr_unit_info->vectorid[0]; @@ -791,7 +791,7 @@ static void ga10b_intr_isr_stall_host2soc_3(struct gk20a *g) const struct nvgpu_device *dev; vectorid = - g->mc.nvgpu_next.intr_unit_info[NVGPU_CIC_INTR_UNIT_CE_STALL].vectorid[0]; + g->mc.intr_unit_info[NVGPU_CIC_INTR_UNIT_CE_STALL].vectorid[0]; handled_subtree_mask |= unit_subtree_mask; ga10b_intr_subtree_clear(g, subtree, unit_subtree_mask); diff --git a/drivers/gpu/nvgpu/hal/netlist/netlist_ga100.c b/drivers/gpu/nvgpu/hal/netlist/netlist_ga100.c index 6146632dd..127bc67d0 100644 --- a/drivers/gpu/nvgpu/hal/netlist/netlist_ga100.c +++ b/drivers/gpu/nvgpu/hal/netlist/netlist_ga100.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2020, NVIDIA CORPORATION. All rights reserved. + * Copyright (c) 2020-2021, NVIDIA CORPORATION. All rights reserved. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), diff --git a/drivers/gpu/nvgpu/hal/power_features/cg/ga100_gating_reglist.c b/drivers/gpu/nvgpu/hal/power_features/cg/ga100_gating_reglist.c index 97aa77c1f..9896335f9 100644 --- a/drivers/gpu/nvgpu/hal/power_features/cg/ga100_gating_reglist.c +++ b/drivers/gpu/nvgpu/hal/power_features/cg/ga100_gating_reglist.c @@ -418,7 +418,7 @@ void ga100_slcg_runlist_load_gating_prod(struct gk20a *g, ga100_slcg_runlist[i].disable; for (j = 0U; j < f->num_runlists; j++) { runlist = &f->active_runlists[j]; - runlist_pri_base = runlist->nvgpu_next.runlist_pri_base; + runlist_pri_base = runlist->runlist_pri_base; nvgpu_writel(g, nvgpu_safe_add_u32(reg, runlist_pri_base), val); } } @@ -776,7 +776,7 @@ void ga100_blcg_runlist_load_gating_prod(struct gk20a *g, ga100_blcg_runlist[i].disable; for (j = 0U; j < f->num_runlists; j++) { runlist = &f->active_runlists[j]; - runlist_pri_base = runlist->nvgpu_next.runlist_pri_base; + runlist_pri_base = runlist->runlist_pri_base; nvgpu_writel(g, nvgpu_safe_add_u32(reg, runlist_pri_base), val); } } diff --git a/drivers/gpu/nvgpu/hal/power_features/cg/ga10b_gating_reglist.c b/drivers/gpu/nvgpu/hal/power_features/cg/ga10b_gating_reglist.c index 70b9f6c5e..f06ffa557 100644 --- a/drivers/gpu/nvgpu/hal/power_features/cg/ga10b_gating_reglist.c +++ b/drivers/gpu/nvgpu/hal/power_features/cg/ga10b_gating_reglist.c @@ -446,7 +446,7 @@ void ga10b_slcg_runlist_load_gating_prod(struct gk20a *g, ga10b_slcg_runlist[i].disable; for (j = 0U; j < f->num_runlists; j++) { runlist = &f->active_runlists[j]; - runlist_pri_base = runlist->nvgpu_next.runlist_pri_base; + runlist_pri_base = runlist->runlist_pri_base; nvgpu_writel(g, nvgpu_safe_add_u32(reg, runlist_pri_base), val); } } @@ -966,7 +966,7 @@ void ga10b_blcg_runlist_load_gating_prod(struct gk20a *g, ga10b_blcg_runlist[i].disable; for (j = 0U; j < f->num_runlists; j++) { runlist = &f->active_runlists[j]; - runlist_pri_base = runlist->nvgpu_next.runlist_pri_base; + runlist_pri_base = runlist->runlist_pri_base; nvgpu_writel(g, nvgpu_safe_add_u32(reg, runlist_pri_base), val); } } diff --git a/drivers/gpu/nvgpu/hal/sim/sim_ga10b.c b/drivers/gpu/nvgpu/hal/sim/sim_ga10b.c new file mode 100644 index 000000000..7fa9250a4 --- /dev/null +++ b/drivers/gpu/nvgpu/hal/sim/sim_ga10b.c @@ -0,0 +1,70 @@ +/* + * Copyright (c) 2021, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "sim_ga10b.h" + +#ifdef CONFIG_NVGPU_SIM +static void nvgpu_sim_esc_readl_ga10b(struct gk20a *g, + const char *path, u32 index, u32 *data) +{ + int err; + u32 data_offset; + + sim_write_hdr(g, sim_msg_function_sim_escape_read_v(), + sim_escape_read_hdr_size()); + *sim_msg_param(g, 0) = index; + *sim_msg_param(g, 4) = sizeof(u32); + data_offset = round_up( + nvgpu_safe_add_u64(strlen(path), 1ULL), sizeof(u32)); + *sim_msg_param(g, 8) = data_offset; + strcpy((char *)sim_msg_param(g, sim_escape_read_hdr_size()), path); + + err = issue_rpc_and_wait(g); + + if (err == 0) { + nvgpu_memcpy((u8 *)data, (u8 *)sim_msg_param(g, + nvgpu_safe_add_u32(data_offset, + sim_escape_read_hdr_size())), + sizeof(u32)); + } else { + *data = 0xffffffff; + WARN(1, "issue_rpc_and_wait failed err=%d", err); + } +} + +void nvgpu_init_sim_support_ga10b(struct gk20a *g) +{ + if (g->sim) { + g->sim->esc_readl = nvgpu_sim_esc_readl_ga10b; + } +} +#endif /* CONFIG_NVGPU_SIM */ diff --git a/drivers/gpu/nvgpu/hal/sim/sim_ga10b.h b/drivers/gpu/nvgpu/hal/sim/sim_ga10b.h new file mode 100644 index 000000000..a09bac175 --- /dev/null +++ b/drivers/gpu/nvgpu/hal/sim/sim_ga10b.h @@ -0,0 +1,33 @@ +/* + * Copyright (c) 2021, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ +#ifndef NVGPU_SIM_GA10B_H +#define NVGPU_SIM_GA10B_H + +#ifdef CONFIG_NVGPU_SIM +struct gk20a; + +void nvgpu_init_sim_support_ga10b(struct gk20a *g); +#endif /* CONFIG_NVGPU_SIM */ + +#endif + + diff --git a/drivers/gpu/nvgpu/hal/top/top_ga10b_fusa.c b/drivers/gpu/nvgpu/hal/top/top_ga10b_fusa.c index 9179b6ad6..6e81dad0e 100644 --- a/drivers/gpu/nvgpu/hal/top/top_ga10b_fusa.c +++ b/drivers/gpu/nvgpu/hal/top/top_ga10b_fusa.c @@ -85,25 +85,25 @@ static struct nvgpu_device *ga10b_top_parse_device(struct gk20a *g, dev->pri_base = top_device_info2_dev_device_pri_base_v(rows[1]) << top_device_info2_dev_device_pri_base_b(); - dev->next.engine = top_device_info2_dev_is_engine_v(rows[1]) == + dev->engine = top_device_info2_dev_is_engine_v(rows[1]) == top_device_info2_dev_is_engine_true_v(); - dev->next.rleng_id = top_device_info2_dev_rleng_id_v(rows[2]); - dev->next.rl_pri_base = + dev->rleng_id = top_device_info2_dev_rleng_id_v(rows[2]); + dev->rl_pri_base = top_device_info2_dev_runlist_pri_base_v(rows[2]) << top_device_info2_dev_runlist_pri_base_b(); - if (dev->next.engine) { + if (dev->engine) { dev->engine_id = g->ops.runlist.get_engine_id_from_rleng_id(g, - dev->next.rleng_id, - dev->next.rl_pri_base); + dev->rleng_id, + dev->rl_pri_base); dev->runlist_id = g->ops.runlist.get_runlist_id(g, - dev->next.rl_pri_base); + dev->rl_pri_base); dev->intr_id = g->ops.runlist.get_engine_intr_id(g, - dev->next.rl_pri_base, - dev->next.rleng_id); + dev->rl_pri_base, + dev->rleng_id); g->ops.runlist.get_pbdma_info(g, - dev->next.rl_pri_base, - &dev->next.pbdma_info); + dev->rl_pri_base, + &dev->pbdma_info); } diff --git a/drivers/gpu/nvgpu/hal/vgpu/init/vgpu_hal_ga10b.c b/drivers/gpu/nvgpu/hal/vgpu/init/vgpu_hal_ga10b.c index d350caac5..9322f6ac6 100644 --- a/drivers/gpu/nvgpu/hal/vgpu/init/vgpu_hal_ga10b.c +++ b/drivers/gpu/nvgpu/hal/vgpu/init/vgpu_hal_ga10b.c @@ -694,7 +694,7 @@ static const struct gops_runlist vgpu_ga10b_ops_runlist = { .get_ch_entry = gv11b_runlist_get_ch_entry, .hw_submit = NULL, .wait_pending = NULL, - .init_enginfo = nvgpu_next_runlist_init_enginfo, + .init_enginfo = nvgpu_runlist_init_enginfo, }; static const struct gops_userd vgpu_ga10b_ops_userd = { diff --git a/drivers/gpu/nvgpu/include/nvgpu/device.h b/drivers/gpu/nvgpu/include/nvgpu/device.h index d6c2d3dec..89b41e949 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/device.h +++ b/drivers/gpu/nvgpu/include/nvgpu/device.h @@ -90,38 +90,6 @@ struct gk20a; #define NVGPU_DEVICE_TOKEN_INIT 0U -#if defined(CONFIG_NVGPU_NON_FUSA) && defined(CONFIG_NVGPU_HAL_NON_FUSA) -struct nvgpu_device_next { - /** - * True if the device is an method engine behind host. - */ - bool engine; - - /** - * Runlist Engine ID; only valid if #engine is true. - */ - u32 rleng_id; - - /** - * Runlist PRI base - byte aligned based address. CHRAM offset can - * be computed from this. - */ - u32 rl_pri_base; - - /** - * PBDMA info for this device. It may contain multiple PBDMAs as - * there can now be multiple PBDMAs per runlist. - * - * This is in some ways awkward; devices seem to be more directly - * linked to runlists; runlists in turn have PBDMAs. Granted that - * means there's a computable relation between devices and PBDMAs - * it may make sense to not have this link. - */ - struct nvgpu_next_pbdma_info pbdma_info; - -}; -#endif - /** * Structure definition for storing information for the devices and the engines * available on the chip. @@ -183,8 +151,34 @@ struct nvgpu_device { /** @cond DOXYGEN_SHOULD_SKIP_THIS */ #if defined(CONFIG_NVGPU_NON_FUSA) - /* nvgpu next device info additions */ - struct nvgpu_device_next next; + /* Ampere+ device info additions */ + + /** + * True if the device is an method engine behind host. + */ + bool engine; + + /** + * Runlist Engine ID; only valid if #engine is true. + */ + u32 rleng_id; + + /** + * Runlist PRI base - byte aligned based address. CHRAM offset can + * be computed from this. + */ + u32 rl_pri_base; + + /** + * PBDMA info for this device. It may contain multiple PBDMAs as + * there can now be multiple PBDMAs per runlist. + * + * This is in some ways awkward; devices seem to be more directly + * linked to runlists; runlists in turn have PBDMAs. Granted that + * means there's a computable relation between devices and PBDMAs + * it may make sense to not have this link. + */ + struct nvgpu_pbdma_info pbdma_info; #endif /** @endcond DOXYGEN_SHOULD_SKIP_THIS */ }; diff --git a/drivers/gpu/nvgpu/include/nvgpu/engine_status.h b/drivers/gpu/nvgpu/include/nvgpu/engine_status.h index 97ad7bb4b..5c82069e8 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/engine_status.h +++ b/drivers/gpu/nvgpu/include/nvgpu/engine_status.h @@ -91,12 +91,6 @@ enum nvgpu_engine_status_ctx_status { NVGPU_CTX_STATUS_CTXSW_SWITCH, }; -#if defined(CONFIG_NVGPU_NON_FUSA) && defined(CONFIG_NVGPU_HAL_NON_FUSA) -struct nvgpu_next_engine_status_info { - /** Engine status_1 h/w register's read value. */ - u32 reg1_data; -}; -#endif struct nvgpu_engine_status_info { /** Engine status h/w register's read value. */ @@ -104,7 +98,9 @@ struct nvgpu_engine_status_info { #if defined(CONFIG_NVGPU_NON_FUSA) /** @cond DOXYGEN_SHOULD_SKIP_THIS */ /* Ampere+ engine status additions */ - struct nvgpu_next_engine_status_info nvgpu_next; + + /** Engine status_1 h/w register's read value. */ + u32 reg1_data; /** @endcond DOXYGEN_SHOULD_SKIP_THIS */ #endif /** Channel or tsg id that is currently assigned to the engine. */ diff --git a/drivers/gpu/nvgpu/include/nvgpu/engines.h b/drivers/gpu/nvgpu/include/nvgpu/engines.h index a3ce8b289..65a1b9a15 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/engines.h +++ b/drivers/gpu/nvgpu/include/nvgpu/engines.h @@ -37,8 +37,8 @@ struct nvgpu_device; #if defined(CONFIG_NVGPU_NON_FUSA) #define ENGINE_PBDMA_INSTANCE0 0U -int nvgpu_next_engine_init_one_dev(struct gk20a *g, - const struct nvgpu_device *dev); +int nvgpu_engine_init_one_dev_extra(struct gk20a *g, + const struct nvgpu_device *dev); #endif /** @endcond DOXYGEN_SHOULD_SKIP_THIS */ diff --git a/drivers/gpu/nvgpu/include/nvgpu/gops/runlist.h b/drivers/gpu/nvgpu/include/nvgpu/gops/runlist.h index 95b892854..37edf14ce 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/gops/runlist.h +++ b/drivers/gpu/nvgpu/include/nvgpu/gops/runlist.h @@ -95,7 +95,7 @@ struct gops_runlist { u32 rleng_id, u32 runlist_pri_base); u32 (*get_chram_bar0_offset)(struct gk20a *g, u32 runlist_pri_base); void (*get_pbdma_info)(struct gk20a *g, u32 runlist_pri_base, - struct nvgpu_next_pbdma_info *pbdma_info); + struct nvgpu_pbdma_info *pbdma_info); u32 (*get_engine_intr_id)(struct gk20a *g, u32 runlist_pri_base, u32 rleng_id); u32 (*get_esched_fb_thread_id)(struct gk20a *g, u32 runlist_pri_base); diff --git a/drivers/gpu/nvgpu/include/nvgpu/mc.h b/drivers/gpu/nvgpu/include/nvgpu/mc.h index 47dc80538..7e402b930 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/mc.h +++ b/drivers/gpu/nvgpu/include/nvgpu/mc.h @@ -184,18 +184,6 @@ struct nvgpu_intr_unit_info { */ bool valid; }; - -struct nvgpu_next_mc { - /** - * intr info array indexed by s/w defined intr unit name - */ - struct nvgpu_intr_unit_info intr_unit_info[NVGPU_CIC_INTR_UNIT_MAX]; - /** - * Leaf mask per subtree. Subtree is a pair of leaf registers. - * Each subtree corresponds to a bit in intr_top register. - */ - u64 subtree_mask_restore[HOST2SOC_NUM_SUBTREE]; -}; #endif /** @@ -252,7 +240,15 @@ struct nvgpu_mc { /** @cond DOXYGEN_SHOULD_SKIP_THIS */ #if defined(CONFIG_NVGPU_NON_FUSA) - struct nvgpu_next_mc nvgpu_next; + /** + * intr info array indexed by s/w defined intr unit name + */ + struct nvgpu_intr_unit_info intr_unit_info[NVGPU_CIC_INTR_UNIT_MAX]; + /** + * Leaf mask per subtree. Subtree is a pair of leaf registers. + * Each subtree corresponds to a bit in intr_top register. + */ + u64 subtree_mask_restore[HOST2SOC_NUM_SUBTREE]; #endif /** @endcond DOXYGEN_SHOULD_SKIP_THIS */ }; diff --git a/drivers/gpu/nvgpu/include/nvgpu/netlist.h b/drivers/gpu/nvgpu/include/nvgpu/netlist.h index eeb5e9874..bebf3293e 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/netlist.h +++ b/drivers/gpu/nvgpu/include/nvgpu/netlist.h @@ -389,6 +389,7 @@ u32 nvgpu_netlist_get_ppc_ctxsw_regs_count(struct gk20a *g); u32 nvgpu_netlist_get_gpc_ctxsw_regs_count(struct gk20a *g); u32 nvgpu_netlist_get_tpc_ctxsw_regs_count(struct gk20a *g); u32 nvgpu_netlist_get_etpc_ctxsw_regs_count(struct gk20a *g); +u32 nvgpu_netlist_get_sys_ctxsw_regs_count(struct gk20a *g); void nvgpu_netlist_print_ctxsw_reg_info(struct gk20a *g); #endif /* CONFIG_NVGPU_DEBUGGER */ @@ -407,60 +408,45 @@ void nvgpu_netlist_vars_set_dynamic(struct gk20a *g, bool set); void nvgpu_netlist_vars_set_buffer_size(struct gk20a *g, u32 size); void nvgpu_netlist_vars_set_regs_base_index(struct gk20a *g, u32 index); -bool nvgpu_next_netlist_handle_sw_bundles_region_id(struct gk20a *g, - u32 region_id, u8 *src, u32 size, - struct nvgpu_netlist_vars *netlist_vars, int *err_code); -void nvgpu_next_netlist_deinit_ctx_vars(struct gk20a *g); -struct netlist_av_list *nvgpu_next_netlist_get_sw_non_ctx_local_compute_load_av_list( +struct netlist_av_list *nvgpu_netlist_get_sw_non_ctx_local_compute_load_av_list( struct gk20a *g); -struct netlist_av_list *nvgpu_next_netlist_get_sw_non_ctx_global_compute_load_av_list( +struct netlist_av_list *nvgpu_netlist_get_sw_non_ctx_global_compute_load_av_list( struct gk20a *g); #ifdef CONFIG_NVGPU_GRAPHICS -struct netlist_av_list *nvgpu_next_netlist_get_sw_non_ctx_local_gfx_load_av_list( +struct netlist_av_list *nvgpu_netlist_get_sw_non_ctx_local_gfx_load_av_list( struct gk20a *g); -struct netlist_av_list *nvgpu_next_netlist_get_sw_non_ctx_global_gfx_load_av_list( +struct netlist_av_list *nvgpu_netlist_get_sw_non_ctx_global_gfx_load_av_list( struct gk20a *g); #endif /* CONFIG_NVGPU_GRAPHICS */ #ifdef CONFIG_NVGPU_DEBUGGER -bool nvgpu_next_netlist_handle_debugger_region_id(struct gk20a *g, - u32 region_id, u8 *src, u32 size, - struct nvgpu_netlist_vars *netlist_vars, int *err_code); -void nvgpu_next_netlist_deinit_ctxsw_regs(struct gk20a *g); - -struct netlist_aiv_list *nvgpu_next_netlist_get_sys_compute_ctxsw_regs( +struct netlist_aiv_list *nvgpu_netlist_get_sys_compute_ctxsw_regs( struct gk20a *g); -struct netlist_aiv_list *nvgpu_next_netlist_get_gpc_compute_ctxsw_regs( +struct netlist_aiv_list *nvgpu_netlist_get_gpc_compute_ctxsw_regs( struct gk20a *g); -struct netlist_aiv_list *nvgpu_next_netlist_get_tpc_compute_ctxsw_regs( +struct netlist_aiv_list *nvgpu_netlist_get_tpc_compute_ctxsw_regs( struct gk20a *g); -struct netlist_aiv_list *nvgpu_next_netlist_get_ppc_compute_ctxsw_regs( +struct netlist_aiv_list *nvgpu_netlist_get_ppc_compute_ctxsw_regs( struct gk20a *g); -struct netlist_aiv_list *nvgpu_next_netlist_get_etpc_compute_ctxsw_regs( +struct netlist_aiv_list *nvgpu_netlist_get_etpc_compute_ctxsw_regs( struct gk20a *g); -struct netlist_aiv_list *nvgpu_next_netlist_get_lts_ctxsw_regs( +struct netlist_aiv_list *nvgpu_netlist_get_lts_ctxsw_regs( struct gk20a *g); #ifdef CONFIG_NVGPU_GRAPHICS -struct netlist_aiv_list *nvgpu_next_netlist_get_sys_gfx_ctxsw_regs( +struct netlist_aiv_list *nvgpu_netlist_get_sys_gfx_ctxsw_regs( struct gk20a *g); -struct netlist_aiv_list *nvgpu_next_netlist_get_gpc_gfx_ctxsw_regs( +struct netlist_aiv_list *nvgpu_netlist_get_gpc_gfx_ctxsw_regs( struct gk20a *g); -struct netlist_aiv_list *nvgpu_next_netlist_get_tpc_gfx_ctxsw_regs( +struct netlist_aiv_list *nvgpu_netlist_get_tpc_gfx_ctxsw_regs( struct gk20a *g); -struct netlist_aiv_list *nvgpu_next_netlist_get_ppc_gfx_ctxsw_regs( +struct netlist_aiv_list *nvgpu_netlist_get_ppc_gfx_ctxsw_regs( struct gk20a *g); -struct netlist_aiv_list *nvgpu_next_netlist_get_etpc_gfx_ctxsw_regs( +struct netlist_aiv_list *nvgpu_netlist_get_etpc_gfx_ctxsw_regs( struct gk20a *g); #endif /* CONFIG_NVGPU_GRAPHICS */ -u32 nvgpu_next_netlist_get_sys_ctxsw_regs_count(struct gk20a *g); -u32 nvgpu_next_netlist_get_ppc_ctxsw_regs_count(struct gk20a *g); -u32 nvgpu_next_netlist_get_gpc_ctxsw_regs_count(struct gk20a *g); -u32 nvgpu_next_netlist_get_tpc_ctxsw_regs_count(struct gk20a *g); -u32 nvgpu_next_netlist_get_etpc_ctxsw_regs_count(struct gk20a *g); -void nvgpu_next_netlist_print_ctxsw_reg_info(struct gk20a *g); #endif /* CONFIG_NVGPU_DEBUGGER */ -#endif +#endif /* CONFIG_NVGPU_NON_FUSA */ /** @endcond DOXYGEN_SHOULD_SKIP_THIS */ #endif /* NVGPU_NETLIST_H */ diff --git a/drivers/gpu/nvgpu/include/nvgpu/pbdma.h b/drivers/gpu/nvgpu/include/nvgpu/pbdma.h index e780ce3b7..25a3ec97c 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/pbdma.h +++ b/drivers/gpu/nvgpu/include/nvgpu/pbdma.h @@ -42,7 +42,7 @@ struct gk20a; #define NVGPU_INVALID_PBDMA_PRI_BASE U32_MAX #define NVGPU_INVALID_PBDMA_ID U32_MAX -struct nvgpu_next_pbdma_info { +struct nvgpu_pbdma_info { /** The pri offset of the i'th PBDMA for runlist_pri_base */ u32 pbdma_pri_base[PBDMA_PER_RUNLIST_SIZE]; /** The ID of the i'th PBDMA that runs channels on this runlist */ diff --git a/drivers/gpu/nvgpu/include/nvgpu/profiler.h b/drivers/gpu/nvgpu/include/nvgpu/profiler.h index 78a89f4a0..e8be009c9 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/profiler.h +++ b/drivers/gpu/nvgpu/include/nvgpu/profiler.h @@ -185,7 +185,7 @@ bool nvgpu_profiler_validate_regops_allowlist(struct nvgpu_profiler_object *prof u32 offset, enum nvgpu_pm_resource_hwpm_register_type *type); #ifdef CONFIG_NVGPU_HAL_NON_FUSA -void nvgpu_next_profiler_hs_stream_quiesce(struct gk20a *g); +void nvgpu_profiler_hs_stream_quiesce(struct gk20a *g); #endif /* CONFIG_NVGPU_HAL_NON_FUSA */ #endif /* CONFIG_NVGPU_PROFILER */ diff --git a/drivers/gpu/nvgpu/include/nvgpu/runlist.h b/drivers/gpu/nvgpu/include/nvgpu/runlist.h index b524309d5..d296a6f6a 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/runlist.h +++ b/drivers/gpu/nvgpu/include/nvgpu/runlist.h @@ -37,11 +37,11 @@ struct gk20a; struct nvgpu_tsg; struct nvgpu_fifo; struct nvgpu_channel; +struct nvgpu_device; /** @cond DOXYGEN_SHOULD_SKIP_THIS */ #if defined(CONFIG_NVGPU_NON_FUSA) -struct nvgpu_next_pbdma_info; -struct nvgpu_device; +struct nvgpu_pbdma_info; #define RLENG_PER_RUNLIST_SIZE 3 #endif @@ -81,22 +81,6 @@ struct nvgpu_device; /** Runlist identifier is invalid. */ #define NVGPU_INVALID_RUNLIST_ID U32_MAX -/** @cond DOXYGEN_SHOULD_SKIP_THIS */ -#if defined(CONFIG_NVGPU_NON_FUSA) -struct nvgpu_next_runlist { - /* Ampere+ runlist info additions */ - - /** Runlist pri base - offset into device's runlist space */ - u32 runlist_pri_base; - /** Channel ram address in bar0 pri space */ - u32 chram_bar0_offset; - /** Pointer to pbdma info stored in engine_info*/ - const struct nvgpu_next_pbdma_info *pbdma_info; - /** Pointer to engine info for per runlist engine id */ - const struct nvgpu_device *rl_dev_list[RLENG_PER_RUNLIST_SIZE]; -}; -#endif - struct nvgpu_runlist { /** Runlist identifier. */ u32 id; @@ -122,7 +106,15 @@ struct nvgpu_runlist { /** @cond DOXYGEN_SHOULD_SKIP_THIS */ #if defined(CONFIG_NVGPU_NON_FUSA) /* Ampere+ runlist info additions */ - struct nvgpu_next_runlist nvgpu_next; + + /** Runlist pri base - offset into device's runlist space */ + u32 runlist_pri_base; + /** Channel ram address in bar0 pri space */ + u32 chram_bar0_offset; + /** Pointer to pbdma info stored in engine_info*/ + const struct nvgpu_pbdma_info *pbdma_info; + /** Pointer to engine info for per runlist engine id */ + const struct nvgpu_device *rl_dev_list[RLENG_PER_RUNLIST_SIZE]; #endif /** @endcond DOXYGEN_SHOULD_SKIP_THIS */ }; @@ -382,10 +374,6 @@ u32 nvgpu_runlist_get_runlists_mask(struct gk20a *g, u32 id, */ void nvgpu_runlist_init_enginfo(struct gk20a *g, struct nvgpu_fifo *f); -#if defined(CONFIG_NVGPU_NON_FUSA) -void nvgpu_next_runlist_init_enginfo(struct gk20a *g, struct nvgpu_fifo *f); -#endif - /** @endcond DOXYGEN_SHOULD_SKIP_THIS */ #define rl_dbg(g, fmt, arg...) \ diff --git a/drivers/gpu/nvgpu/include/nvgpu/sim.h b/drivers/gpu/nvgpu/include/nvgpu/sim.h index a82d1d32a..10293457e 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/sim.h +++ b/drivers/gpu/nvgpu/include/nvgpu/sim.h @@ -105,18 +105,9 @@ static inline u32 *sim_msg_param(struct gk20a *g, u32 byte_offset) } /** @cond DOXYGEN_SHOULD_SKIP_THIS */ -#if defined(CONFIG_NVGPU_NON_FUSA) && defined(CONFIG_NVGPU_HAL_NON_FUSA) -void nvgpu_next_init_sim_support(struct gk20a *g); - -#ifdef CONFIG_NVGPU_DEBUGGER -int nvgpu_next_init_sim_netlist_ctxsw_regs(struct gk20a *g); -void nvgpu_next_init_sim_netlist_ctxsw_regs_free(struct gk20a *g); -#endif /* CONFIG_NVGPU_DEBUGGER */ - -int nvgpu_next_init_sim_netlist_ctx_vars(struct gk20a *g); -void nvgpu_next_init_sim_netlist_ctx_vars_free(struct gk20a *g); - -#endif +#ifdef CONFIG_NVGPU_NON_FUSA +void nvgpu_init_sim_support2(struct gk20a *g); +#endif /* CONFIG_NVGPU_NON_FUSA */ /** @endcond DOXYGEN_SHOULD_SKIP_THIS */ #endif diff --git a/drivers/gpu/nvgpu/nvgpu_next_gpuid.h b/drivers/gpu/nvgpu/nvgpu_next_gpuid.h index 428056282..f18d88dec 100644 --- a/drivers/gpu/nvgpu/nvgpu_next_gpuid.h +++ b/drivers/gpu/nvgpu/nvgpu_next_gpuid.h @@ -41,7 +41,7 @@ #define NVGPU_NEXT_VGPU_INIT_HAL vgpu_ga10b_init_hal #define NVGPU_NEXT_PLATFORM_VGPU ga10b_vgpu_tegra_platform -#define NVGPU_NEXT_PROFILER_QUIESCE nvgpu_next_profiler_hs_stream_quiesce +#define NVGPU_NEXT_PROFILER_QUIESCE nvgpu_profiler_hs_stream_quiesce #ifdef CONFIG_NVGPU_DGPU #define NVGPU_NEXT_DGPU_GPUID 0x00000170 #define NVGPU_NEXT_DGPU_INIT_HAL ga100_init_hal @@ -57,14 +57,14 @@ extern int ga10b_init_hal(struct gk20a *g); extern struct gk20a_platform ga10b_tegra_platform; -extern void nvgpu_next_perfmon_sw_init(struct gk20a *g, +extern void nvgpu_ga10b_perfmon_sw_init(struct gk20a *g, struct nvgpu_pmu_perfmon *perfmon); -extern void nvgpu_next_pg_sw_init(struct gk20a *g, struct nvgpu_pmu_pg *pg); +extern void nvgpu_ga10b_pg_sw_init(struct gk20a *g, struct nvgpu_pmu_pg *pg); int vgpu_ga10b_init_hal(struct gk20a *g); extern struct gk20a_platform ga10b_vgpu_tegra_platform; -extern void nvgpu_next_profiler_hs_stream_quiesce(struct gk20a *g); +extern void nvgpu_profiler_hs_stream_quiesce(struct gk20a *g); #endif diff --git a/drivers/gpu/nvgpu/os/linux/ioctl_prof.h b/drivers/gpu/nvgpu/os/linux/ioctl_prof.h index 596a7a3bd..b62442d86 100644 --- a/drivers/gpu/nvgpu/os/linux/ioctl_prof.h +++ b/drivers/gpu/nvgpu/os/linux/ioctl_prof.h @@ -29,9 +29,5 @@ int nvgpu_prof_ctx_fops_open(struct inode *inode, struct file *filp); int nvgpu_prof_fops_release(struct inode *inode, struct file *filp); long nvgpu_prof_fops_ioctl(struct file *filp, unsigned int cmd, unsigned long arg); -#if defined(CONFIG_NVGPU_NON_FUSA) -int nvgpu_next_prof_fops_ioctl(struct nvgpu_profiler_object *prof, - unsigned int cmd, void *buf); -#endif #endif /* LINUX_IOCTL_PROF_H */