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gpu: nvgpu: remove NVGPU_GR_NUM_INSTANCES

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common.gr defined a temporary macro NVGPU_GR_NUM_INSTANCES to enable or
disable multiple GR instances from common.gr unit.
Multiple GR instance boot is now verified, so we can remove this
temporary solution.

Note that nvgpu_grmgr_get_num_gr_instances() will return more than 1
instance only if NVGPU_SUPPORT_MIG is enabled.

Update unit tests to set number of syspipes to 1 to allow enumeration
of GR instance by grmgr.

Jira NVGPU-5648

Change-Id: I795901ae516843ae7b6c1794dae0f023a213ab1d
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2418377
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This commit is contained in:
Deepak Nibade
2020-09-23 12:29:57 +05:30
committed by Alex Waterman
parent b9050c51c1
commit d2bb5df3c7
5 changed files with 5 additions and 12 deletions
Download Patch File Download Diff File Expand all files Collapse all files

11
drivers/gpu/nvgpu/common/gr/gr.c
View File

@@ -53,14 +53,6 @@
#include "gr_priv.h" #include "gr_priv.h"
/*
* Use this until common.gr is completely updated to support multiple
* GR instances. Once that is supported, nvgpu_grmgr_get_num_gr_instances()
* should be used to get number of GR instances.
* Set this to 0 for local MIG testing.
*/
#define NVGPU_GR_NUM_INSTANCES 1
static int gr_alloc_global_ctx_buffers(struct gk20a *g, struct nvgpu_gr *gr) static int gr_alloc_global_ctx_buffers(struct gk20a *g, struct nvgpu_gr *gr)
{ {
int err; int err;
@@ -875,10 +867,7 @@ int nvgpu_gr_alloc(struct gk20a *g)
return 0; return 0;
} }
g->num_gr_instances = NVGPU_GR_NUM_INSTANCES;
if (g->num_gr_instances == 0U) {
g->num_gr_instances = nvgpu_grmgr_get_num_gr_instances(g); g->num_gr_instances = nvgpu_grmgr_get_num_gr_instances(g);
}
if (g->num_gr_instances == 0U) { if (g->num_gr_instances == 0U) {
nvgpu_err(g, "No GR engine enumerated"); nvgpu_err(g, "No GR engine enumerated");
return -EINVAL; return -EINVAL;

1
userspace/units/acr/nvgpu-acr.c
View File

@@ -180,6 +180,7 @@ static void nvgpu_init_gr_manager(struct gk20a *g)
struct nvgpu_gr_syspipe *gr_syspipe = &gpu_instance->gr_syspipe; struct nvgpu_gr_syspipe *gr_syspipe = &gpu_instance->gr_syspipe;
g->mig.num_gpu_instances = 1; g->mig.num_gpu_instances = 1;
g->mig.num_gr_sys_pipes_enabled = 1;
gr_syspipe->gr_instance_id = 0U; gr_syspipe->gr_instance_id = 0U;
gr_syspipe->gr_syspipe_id = 0U; gr_syspipe->gr_syspipe_id = 0U;
} }

1
userspace/units/gr/nvgpu-gr.c
View File

@@ -47,6 +47,7 @@ static void nvgpu_init_gr_manager(struct gk20a *g)
struct nvgpu_gr_syspipe *gr_syspipe = &gpu_instance->gr_syspipe; struct nvgpu_gr_syspipe *gr_syspipe = &gpu_instance->gr_syspipe;
g->mig.num_gpu_instances = 1; g->mig.num_gpu_instances = 1;
g->mig.num_gr_sys_pipes_enabled = 1;
gr_syspipe->gr_instance_id = 0U; gr_syspipe->gr_instance_id = 0U;
gr_syspipe->gr_syspipe_id = 0U; gr_syspipe->gr_syspipe_id = 0U;
} }

1
userspace/units/ltc/nvgpu-ltc.c
View File

@@ -248,6 +248,7 @@ static void nvgpu_init_gr_manager(struct gk20a *g)
struct nvgpu_gr_syspipe *gr_syspipe = &gpu_instance->gr_syspipe; struct nvgpu_gr_syspipe *gr_syspipe = &gpu_instance->gr_syspipe;
g->mig.num_gpu_instances = 1; g->mig.num_gpu_instances = 1;
g->mig.num_gr_sys_pipes_enabled = 1;
gr_syspipe->gr_instance_id = 0U; gr_syspipe->gr_instance_id = 0U;
gr_syspipe->gr_syspipe_id = 0U; gr_syspipe->gr_syspipe_id = 0U;
} }

1
userspace/units/pmu/nvgpu-pmu.c
View File

@@ -168,6 +168,7 @@ static void nvgpu_init_gr_manager(struct gk20a *g)
struct nvgpu_gr_syspipe *gr_syspipe = &gpu_instance->gr_syspipe; struct nvgpu_gr_syspipe *gr_syspipe = &gpu_instance->gr_syspipe;
g->mig.num_gpu_instances = 1; g->mig.num_gpu_instances = 1;
g->mig.num_gr_sys_pipes_enabled = 1;
gr_syspipe->gr_instance_id = 0U; gr_syspipe->gr_instance_id = 0U;
gr_syspipe->gr_syspipe_id = 0U; gr_syspipe->gr_syspipe_id = 0U;
} }