gpu: nvgpu: prepare MCLK/GPCLK enumeration change

GPC2CLK has been replaced with GPCCLK on user API.
Remove related definition from kernel API.
GPCLCK and MCLK are currently assigned EQU values in kernel API.
We want to move to a simple enumeration as used in nvrm_gpu.
During the transition, an alias value will be defined for each
clock, and kernel will accept both.

Jira DNVGPU-210
Jira DNVGPU-211

Change-Id: I944fe78be9f810279f7a69964be7cda9b9c8d40d
Signed-off-by: Thomas Fleury <tfleury@nvidia.com>
Reviewed-on: http://git-master/r/1292593
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>

drivers/gpu/nvgpu/clk/clk_arb.c

@@ -313,7 +313,7 @@ int nvgpu_clk_arb_init_arbiter(struct gk20a *g)
 	spin_lock_init(&arb->users_lock);
 
 	err =  g->ops.clk_arb.get_arbiter_clk_default(g,
-			NVGPU_GPU_CLK_DOMAIN_MCLK, &default_mhz);
+			CTRL_CLK_DOMAIN_MCLK, &default_mhz);
 	if (err < 0) {
 		err = -EINVAL;
 		goto init_fail;
@@ -322,7 +322,7 @@ int nvgpu_clk_arb_init_arbiter(struct gk20a *g)
 	arb->mclk_default_mhz = default_mhz;
 
 	err =  g->ops.clk_arb.get_arbiter_clk_default(g,
-			NVGPU_GPU_CLK_DOMAIN_GPC2CLK, &default_mhz);
+			CTRL_CLK_DOMAIN_GPC2CLK, &default_mhz);
 	if (err < 0) {
 		err = -EINVAL;
 		goto init_fail;
@@ -672,14 +672,13 @@ static int nvgpu_clk_arb_update_vf_table(struct nvgpu_clk_arb *arb)
 		&arb->vf_table_pool[0];
 
 	/* Get allowed memory ranges */
-	if (nvgpu_clk_arb_get_arbiter_clk_range(g, NVGPU_GPU_CLK_DOMAIN_GPC2CLK,
-						&gpc2clk_min,
-						&gpc2clk_max) < 0) {
+	if (g->ops.clk_arb.get_arbiter_clk_range(g, CTRL_CLK_DOMAIN_GPC2CLK,
+			&gpc2clk_min, &gpc2clk_max) < 0) {
 		gk20a_err(dev_from_gk20a(g),
 			"failed to fetch GPC2CLK range");
 		goto exit_vf_table;
 	}
-	if (nvgpu_clk_arb_get_arbiter_clk_range(g, NVGPU_GPU_CLK_DOMAIN_MCLK,
+	if (g->ops.clk_arb.get_arbiter_clk_range(g, CTRL_CLK_DOMAIN_MCLK,
 			&mclk_min, &mclk_max) < 0) {
 		gk20a_err(dev_from_gk20a(g),
 			"failed to fetch MCLK range");
@@ -689,14 +688,14 @@ static int nvgpu_clk_arb_update_vf_table(struct nvgpu_clk_arb *arb)
 	table->gpc2clk_num_points = MAX_F_POINTS;
 	table->mclk_num_points = MAX_F_POINTS;
 
-	if (clk_domain_get_f_points(arb->g, NVGPU_GPU_CLK_DOMAIN_GPC2CLK,
+	if (clk_domain_get_f_points(arb->g, CTRL_CLK_DOMAIN_GPC2CLK,
 		&table->gpc2clk_num_points, arb->gpc2clk_f_points)) {
 		gk20a_err(dev_from_gk20a(g),
 			"failed to fetch GPC2CLK frequency points");
 		goto exit_vf_table;
 	}
 
-	if (clk_domain_get_f_points(arb->g, NVGPU_GPU_CLK_DOMAIN_MCLK,
+	if (clk_domain_get_f_points(arb->g, CTRL_CLK_DOMAIN_MCLK,
 		&table->mclk_num_points, arb->mclk_f_points)) {
 		gk20a_err(dev_from_gk20a(g),
 			"failed to fetch MCLK frequency points");
@@ -1629,17 +1628,15 @@ int nvgpu_clk_arb_set_session_target_mhz(struct nvgpu_clk_session *session,
 
 	switch (api_domain) {
 	case NVGPU_GPU_CLK_DOMAIN_MCLK:
+	case NVGPU_GPU_CLK_DOMAIN_MCLK_ALIAS:
 		dev->mclk_target_mhz = target_mhz;
 		break;
 
 	case NVGPU_GPU_CLK_DOMAIN_GPCCLK:
+	case NVGPU_GPU_CLK_DOMAIN_GPCCLK_ALIAS:
 		dev->gpc2clk_target_mhz = target_mhz * 2ULL;
 		break;
 
-	case NVGPU_GPU_CLK_DOMAIN_GPC2CLK:
-		dev->gpc2clk_target_mhz = target_mhz;
-		break;
-
 	default:
 		err = -EINVAL;
 	}
@@ -1662,17 +1659,15 @@ int nvgpu_clk_arb_get_session_target_mhz(struct nvgpu_clk_session *session,
 
 		switch (api_domain) {
 		case NVGPU_GPU_CLK_DOMAIN_MCLK:
+		case NVGPU_GPU_CLK_DOMAIN_MCLK_ALIAS:
 			*freq_mhz = target->mclk;
 			break;
 
 		case NVGPU_GPU_CLK_DOMAIN_GPCCLK:
+		case NVGPU_GPU_CLK_DOMAIN_GPCCLK_ALIAS:
 			*freq_mhz = target->gpc2clk / 2ULL;
 			break;
 
-		case NVGPU_GPU_CLK_DOMAIN_GPC2CLK:
-			*freq_mhz = target->gpc2clk;
-			break;
-
 		default:
 			*freq_mhz = 0;
 			err = -EINVAL;
@@ -1695,17 +1690,15 @@ int nvgpu_clk_arb_get_arbiter_actual_mhz(struct gk20a *g,
 
 		switch (api_domain) {
 		case NVGPU_GPU_CLK_DOMAIN_MCLK:
+		case NVGPU_GPU_CLK_DOMAIN_MCLK_ALIAS:
 			*freq_mhz = actual->mclk;
 			break;
 
 		case NVGPU_GPU_CLK_DOMAIN_GPCCLK:
+		case NVGPU_GPU_CLK_DOMAIN_GPCCLK_ALIAS:
 			*freq_mhz = actual->gpc2clk / 2ULL;
 			break;
 
-		case NVGPU_GPU_CLK_DOMAIN_GPC2CLK:
-			*freq_mhz = actual->gpc2clk;
-			break;
-
 		default:
 			*freq_mhz = 0;
 			err = -EINVAL;
@@ -1717,12 +1710,20 @@ int nvgpu_clk_arb_get_arbiter_actual_mhz(struct gk20a *g,
 int nvgpu_clk_arb_get_arbiter_effective_mhz(struct gk20a *g,
 		u32 api_domain, u16 *freq_mhz)
 {
-	if (api_domain == NVGPU_GPU_CLK_DOMAIN_GPCCLK)
-		*freq_mhz = g->ops.clk.get_rate(g,
-				NVGPU_GPU_CLK_DOMAIN_GPC2CLK) / 2;
-	else
-		*freq_mhz = g->ops.clk.get_rate(g, api_domain);
+	switch(api_domain) {
+	case NVGPU_GPU_CLK_DOMAIN_MCLK:
+	case NVGPU_GPU_CLK_DOMAIN_MCLK_ALIAS:
+		*freq_mhz = g->ops.clk.get_rate(g, CTRL_CLK_DOMAIN_MCLK);
 		return 0;
+
+	case NVGPU_GPU_CLK_DOMAIN_GPCCLK:
+	case NVGPU_GPU_CLK_DOMAIN_GPCCLK_ALIAS:
+		*freq_mhz = g->ops.clk.get_rate(g, CTRL_CLK_DOMAIN_GPC2CLK) / 2;
+		return 0;
+
+	default:
+		return -EINVAL;
+	}
 }
 
 int nvgpu_clk_arb_get_arbiter_clk_range(struct gk20a *g, u32 api_domain,
@@ -1730,30 +1731,58 @@ int nvgpu_clk_arb_get_arbiter_clk_range(struct gk20a *g, u32 api_domain,
 {
 	int ret;
 
-	if (api_domain == NVGPU_GPU_CLK_DOMAIN_GPCCLK) {
+	switch(api_domain) {
+	case NVGPU_GPU_CLK_DOMAIN_MCLK:
+	case NVGPU_GPU_CLK_DOMAIN_MCLK_ALIAS:
 		ret = g->ops.clk_arb.get_arbiter_clk_range(g,
-				NVGPU_GPU_CLK_DOMAIN_GPC2CLK,
-				min_mhz, max_mhz);
+				CTRL_CLK_DOMAIN_MCLK, min_mhz, max_mhz);
+		return ret;
+
+	case NVGPU_GPU_CLK_DOMAIN_GPCCLK:
+	case NVGPU_GPU_CLK_DOMAIN_GPCCLK_ALIAS:
+		ret = g->ops.clk_arb.get_arbiter_clk_range(g,
+				CTRL_CLK_DOMAIN_GPC2CLK, min_mhz, max_mhz);
 		if (!ret) {
 			*min_mhz /= 2;
 			*max_mhz /= 2;
 		}
-	} else {
-		ret = g->ops.clk_arb.get_arbiter_clk_range(g, api_domain,
-			min_mhz, max_mhz);
-	}
-
 		return ret;
+
+	default:
+		return -EINVAL;
+	}
 }
 
 u32 nvgpu_clk_arb_get_arbiter_clk_domains(struct gk20a *g)
 {
 	u32 clk_domains = g->ops.clk_arb.get_arbiter_clk_domains(g);
+	u32 api_domains = 0;
 
 	if (clk_domains & CTRL_CLK_DOMAIN_GPC2CLK)
-		clk_domains |= CTRL_CLK_DOMAIN_GPCCLK;
+		api_domains |= NVGPU_GPU_CLK_DOMAIN_GPCCLK_ALIAS;
 
-	return clk_domains;
+	if (clk_domains & CTRL_CLK_DOMAIN_MCLK)
+		api_domains |= NVGPU_GPU_CLK_DOMAIN_MCLK_ALIAS;
+
+	return api_domains;
+}
+
+bool nvgpu_clk_arb_is_valid_domain(struct gk20a *g, u32 api_domain)
+{
+	u32 clk_domains = g->ops.clk_arb.get_arbiter_clk_domains(g);
+
+	switch(api_domain) {
+	case NVGPU_GPU_CLK_DOMAIN_MCLK:
+	case NVGPU_GPU_CLK_DOMAIN_MCLK_ALIAS:
+		return ((clk_domains & CTRL_CLK_DOMAIN_MCLK) != 0);
+
+	case NVGPU_GPU_CLK_DOMAIN_GPCCLK:
+	case NVGPU_GPU_CLK_DOMAIN_GPCCLK_ALIAS:
+		return ((clk_domains & CTRL_CLK_DOMAIN_GPC2CLK) != 0);
+
+	default:
+		return false;
+	}
 }
 
 int nvgpu_clk_arb_get_arbiter_clk_f_points(struct gk20a *g,
@@ -1762,19 +1791,23 @@ int nvgpu_clk_arb_get_arbiter_clk_f_points(struct gk20a *g,
 	int err;
 	u32 i;
 
-	if (api_domain == NVGPU_GPU_CLK_DOMAIN_GPCCLK) {
-		err = clk_domain_get_f_points(g, NVGPU_GPU_CLK_DOMAIN_GPC2CLK,
+	switch (api_domain) {
+	case NVGPU_GPU_CLK_DOMAIN_GPCCLK:
+	case NVGPU_GPU_CLK_DOMAIN_GPCCLK_ALIAS:
+		err = clk_domain_get_f_points(g, CTRL_CLK_DOMAIN_GPC2CLK,
 				max_points, fpoints);
 		if (err || !fpoints)
 			return err;
 		for (i = 0; i < *max_points; i++)
 			fpoints[i] /= 2;
-	} else {
-		err = clk_domain_get_f_points(g, api_domain,
+		return 0;
+	case NVGPU_GPU_CLK_DOMAIN_MCLK:
+	case NVGPU_GPU_CLK_DOMAIN_MCLK_ALIAS:
+		return clk_domain_get_f_points(g, CTRL_CLK_DOMAIN_MCLK,
 				max_points, fpoints);
+	default:
+		return -EINVAL;
 	}
-
-	return err;
 }
 
 static u8 nvgpu_clk_arb_find_vf_point(struct nvgpu_clk_arb *arb,

drivers/gpu/nvgpu/clk/clk_arb.h

@@ -34,6 +34,7 @@ int nvgpu_clk_arb_get_arbiter_clk_f_points(struct gk20a *g,
 	u32 api_domain, u32 *max_points, u16 *fpoints);
 
 u32 nvgpu_clk_arb_get_arbiter_clk_domains(struct gk20a *g);
+bool nvgpu_clk_arb_is_valid_domain(struct gk20a *g, u32 api_domain);
 
 void nvgpu_clk_arb_cleanup_arbiter(struct gk20a *g);
 

drivers/gpu/nvgpu/gk20a/ctrl_gk20a.c

@@ -869,7 +869,7 @@ static int nvgpu_gpu_clk_get_vf_points(struct gk20a *g,
 	clk_domains = nvgpu_clk_arb_get_arbiter_clk_domains(g);
 	args->num_entries = 0;
 
-	if ((args->clk_domain & clk_domains) == 0)
+	if (!nvgpu_clk_arb_is_valid_domain(g, args->clk_domain))
 		return -EINVAL;
 
 	err = nvgpu_clk_arb_get_arbiter_clk_f_points(g,
@@ -987,6 +987,9 @@ static int nvgpu_gpu_clk_get_range(struct gk20a *g,
 				return -EFAULT;
 		} else {
 			bit = ffs(clk_domains) - 1;
+			if (bit <= NVGPU_GPU_CLK_DOMAIN_GPCCLK)
+				clk_range.clk_domain = bit;
+			else
 				clk_range.clk_domain = BIT(bit);
 			clk_domains &= ~BIT(bit);
 		}
@@ -1031,6 +1034,8 @@ static int nvgpu_gpu_clk_set_info(struct gk20a *g,
 	if (!session || args->flags)
 		return -EINVAL;
 
+	gk20a_dbg_info("line=%d", __LINE__);
+
 	clk_domains = nvgpu_clk_arb_get_arbiter_clk_domains(g);
 	if (!clk_domains)
 		return -EINVAL;
@@ -1038,15 +1043,17 @@ static int nvgpu_gpu_clk_set_info(struct gk20a *g,
 	entry = (struct nvgpu_gpu_clk_info __user *)
 			(uintptr_t)args->clk_info_entries;
 
+	gk20a_dbg_info("line=%d", __LINE__);
+
 	for (i = 0; i < args->num_entries; i++, entry++) {
 
+	gk20a_dbg_info("line=%d", __LINE__);
 		if (copy_from_user(&clk_info, entry, sizeof(clk_info)))
 			return -EFAULT;
 
-		if ((clk_info.clk_domain & clk_domains) != clk_info.clk_domain)
-			return -EINVAL;
+	gk20a_dbg_info("i=%d domain=0x%08x", i, clk_info.clk_domain);
 
-		if (hweight_long(clk_info.clk_domain) != 1)
+		if (!nvgpu_clk_arb_is_valid_domain(g, clk_info.clk_domain))
 			return -EINVAL;
 	}
 
@@ -1132,6 +1139,9 @@ static int nvgpu_gpu_clk_get_info(struct gk20a *g,
 				return -EFAULT;
 		} else {
 			bit = ffs(clk_domains) - 1;
+			if (bit <= NVGPU_GPU_CLK_DOMAIN_GPCCLK)
+				clk_info.clk_domain = bit;
+			else
 				clk_info.clk_domain = BIT(bit);
 			clk_domains &= ~BIT(bit);
 			clk_info.clk_type = args->clk_type;

include/uapi/linux/nvgpu.h

@@ -537,14 +537,12 @@ struct nvgpu_gpu_alloc_vidmem_args {
 	};
 };
 
-/* Main graphics core clock */
-#define NVGPU_GPU_CLK_DOMAIN_GPCCLK                              (0x10000000)
 /* Memory clock */
-#define NVGPU_GPU_CLK_DOMAIN_MCLK                                (0x00000010)
-/* Main graphics core clock x 2
- *	deprecated, use NVGPU_GPU_CLK_DOMAIN_GPCCLK instead
- */
-#define NVGPU_GPU_CLK_DOMAIN_GPC2CLK                             (0x00010000)
+#define NVGPU_GPU_CLK_DOMAIN_MCLK                                (0)
+#define NVGPU_GPU_CLK_DOMAIN_MCLK_ALIAS                          (0x00000010)
+/* Main graphics core clock */
+#define NVGPU_GPU_CLK_DOMAIN_GPCCLK	                         (1)
+#define NVGPU_GPU_CLK_DOMAIN_GPCCLK_ALIAS                        (0x10000000)
 
 struct nvgpu_gpu_clk_range {