From d328bff79e121f640245054876748bda24698d93 Mon Sep 17 00:00:00 2001 From: Ramesh Mylavarapu Date: Mon, 5 Jul 2021 21:29:37 +0530 Subject: [PATCH] gpu: nvgpu: gsp NVRISCV load and bootstrap Changes: - This change will only init gsp software state, nvgpu_gsp_bootstrap need to be called. - CONFIG_NVGPU_GSP_SCHEDULER flag is created to compile out the gsp scheduler code when needed. - Created GSP engine reset which is needed when ACR completed execution and need to load gsp fw. NVGPU-6783 Signed-off-by: Ramesh Mylavarapu Change-Id: I2ce43e512b01df59443559eab621ed39868ad158 Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2554267 Tested-by: mobile promotions Reviewed-by: mobile promotions --- arch/nvgpu-common.yaml | 10 + drivers/gpu/nvgpu/Makefile | 10 + drivers/gpu/nvgpu/Makefile.linux.configs | 6 + drivers/gpu/nvgpu/Makefile.shared.configs | 3 + drivers/gpu/nvgpu/Makefile.sources | 5 + .../gpu/nvgpu/common/falcon/falcon_sw_ga10b.c | 25 +- drivers/gpu/nvgpu/common/gsp/gsp_bootstrap.c | 251 ++++++++++++++++++ drivers/gpu/nvgpu/common/gsp/gsp_bootstrap.h | 31 +++ drivers/gpu/nvgpu/common/gsp/gsp_init.c | 85 ++++++ drivers/gpu/nvgpu/common/gsp/gsp_priv.h | 38 +++ drivers/gpu/nvgpu/common/init/nvgpu_init.c | 5 + drivers/gpu/nvgpu/hal/gsp/gsp_ga10b.c | 13 +- drivers/gpu/nvgpu/hal/gsp/gsp_ga10b.h | 3 +- drivers/gpu/nvgpu/hal/init/hal_ga10b.c | 1 + drivers/gpu/nvgpu/include/nvgpu/gk20a.h | 7 + drivers/gpu/nvgpu/include/nvgpu/gsp.h | 30 +++ .../include/nvgpu/hw/ga10b/hw_pgsp_ga10b.h | 3 + drivers/gpu/nvgpu/os/linux/module.c | 8 + 18 files changed, 531 insertions(+), 3 deletions(-) create mode 100644 drivers/gpu/nvgpu/common/gsp/gsp_bootstrap.c create mode 100644 drivers/gpu/nvgpu/common/gsp/gsp_bootstrap.h create mode 100644 drivers/gpu/nvgpu/common/gsp/gsp_init.c create mode 100644 drivers/gpu/nvgpu/common/gsp/gsp_priv.h create mode 100644 drivers/gpu/nvgpu/include/nvgpu/gsp.h diff --git a/arch/nvgpu-common.yaml b/arch/nvgpu-common.yaml index 025010352..de1caa354 100644 --- a/arch/nvgpu-common.yaml +++ b/arch/nvgpu-common.yaml @@ -301,6 +301,16 @@ sbr: include/nvgpu/sbr.h, include/nvgpu/gops/sbr.h ] +gsp: + safe: no + owner: Ramesh M + gpu: igpu + sources: [ common/gsp/gsp_init.c, + common/gsp/gsp_priv.h, + common/gsp/gsp_bootstrap.c, + common/gsp/gsp_bootstrap.h, + include/nvgpu/gsp.h ] + engine_queues: owner: Sagar K children: diff --git a/drivers/gpu/nvgpu/Makefile b/drivers/gpu/nvgpu/Makefile index 8863b432f..38e0b4fdf 100644 --- a/drivers/gpu/nvgpu/Makefile +++ b/drivers/gpu/nvgpu/Makefile @@ -74,6 +74,10 @@ ccflags-y += -DCONFIG_NVGPU_SW_SEMAPHORE ccflags-y += -DCONFIG_NVGPU_FENCE ccflags-y += -DCONFIG_NVGPU_PROFILER +ifeq ($(CONFIG_NVGPU_GSP_SCHEDULER),y) +ccflags-y += -DCONFIG_NVGPU_GSP_SCHEDULER +endif + ifeq ($(CONFIG_NVGPU_LOGGING),y) ccflags-y += -DCONFIG_NVGPU_LOGGING=1 endif @@ -397,6 +401,12 @@ nvgpu-y += \ hal/cic/mon/init_gv11b_fusa.o \ hal/cic/mon/lut_gv11b_fusa.o +ifeq ($(CONFIG_NVGPU_GSP_SCHEDULER),y) +nvgpu-$(CONFIG_NVGPU_GSP_SCHEDULER) += \ + common/gsp/gsp_init.o \ + common/gsp/gsp_bootstrap.o +endif + # Linux specific parts of nvgpu. nvgpu-y += \ os/linux/os_ops.o \ diff --git a/drivers/gpu/nvgpu/Makefile.linux.configs b/drivers/gpu/nvgpu/Makefile.linux.configs index be42b79fe..b45940975 100644 --- a/drivers/gpu/nvgpu/Makefile.linux.configs +++ b/drivers/gpu/nvgpu/Makefile.linux.configs @@ -43,6 +43,9 @@ endif # Support for remap CONFIG_NVGPU_REMAP := y +# Enable gsp scheduler support +CONFIG_NVGPU_GSP_SCHEDULER := y + ifeq ($(CONFIG_COMMON_CLK),y) ifeq ($(CONFIG_PM_DEVFREQ),y) # Select this entry to enable gk20a scaling @@ -232,3 +235,6 @@ endif ifeq ($(CONFIG_NVGPU_SYNCFD_NONE),y) ccflags-y += -DCONFIG_NVGPU_SYNCFD_NONE endif +ifeq ($(CONFIG_NVGPU_GSP_SCHEDULER),y) +ccflags-y += -DCONFIG_NVGPU_GSP_SCHEDULER +endif diff --git a/drivers/gpu/nvgpu/Makefile.shared.configs b/drivers/gpu/nvgpu/Makefile.shared.configs index e55025a21..ccc3f0d34 100644 --- a/drivers/gpu/nvgpu/Makefile.shared.configs +++ b/drivers/gpu/nvgpu/Makefile.shared.configs @@ -295,6 +295,9 @@ NVGPU_COMMON_CFLAGS += -DCONFIG_NVGPU_SM_DIVERSITY CONFIG_NVGPU_MIG := 1 NVGPU_COMMON_CFLAGS += -DCONFIG_NVGPU_MIG +# Enable gsp scheduler for normal build +CONFIG_NVGPU_GSP_SCHEDULER......:= 1 +NVGPU_COMMON_CFLAGS.............+= -DCONFIG_NVGPU_GSP_SCHEDULER endif endif diff --git a/drivers/gpu/nvgpu/Makefile.sources b/drivers/gpu/nvgpu/Makefile.sources index 67556bf04..2cb5e41ba 100644 --- a/drivers/gpu/nvgpu/Makefile.sources +++ b/drivers/gpu/nvgpu/Makefile.sources @@ -176,6 +176,11 @@ srcs += common/device.c \ hal/fifo/userd_gk20a.c \ hal/sync/syncpt_cmdbuf_gv11b.c +ifeq ($(CONFIG_NVGPU_GSP_SCHEDULER),1) +srcs += common/gsp/gsp_init.c \ + common/gsp/gsp_bootstrap.c +endif + # Source files below are functionaly safe (FuSa) and must always be included. srcs += hal/mm/mm_gv11b_fusa.c \ hal/mm/mm_gp10b_fusa.c \ diff --git a/drivers/gpu/nvgpu/common/falcon/falcon_sw_ga10b.c b/drivers/gpu/nvgpu/common/falcon/falcon_sw_ga10b.c index 2ebb0c197..091307ef3 100644 --- a/drivers/gpu/nvgpu/common/falcon/falcon_sw_ga10b.c +++ b/drivers/gpu/nvgpu/common/falcon/falcon_sw_ga10b.c @@ -119,6 +119,29 @@ static void check_and_enable_falcon2(struct nvgpu_falcon *flcn, } } +static void ga10b_falcon_engine_dependency_ops(struct nvgpu_falcon *flcn) +{ + struct gk20a *g = flcn->g; + struct nvgpu_falcon_engine_dependency_ops *flcn_eng_dep_ops = + &flcn->flcn_engine_dep_ops; + + switch (flcn->flcn_id) { + case FALCON_ID_PMU: + gk20a_falcon_engine_dependency_ops(flcn); + break; + case FALCON_ID_GSPLITE: + flcn_eng_dep_ops->reset_eng = g->ops.gsp.gsp_reset; + break; + default: + /* NULL assignment make sure + * CPU hard reset in gk20a_falcon_reset() gets execute + * if falcon doesn't need specific reset implementation + */ + flcn_eng_dep_ops->reset_eng = NULL; + break; + } +} + extern void ga10b_falcon_sw_init(struct nvgpu_falcon *flcn) { struct gk20a *g = flcn->g; @@ -150,7 +173,7 @@ extern void ga10b_falcon_sw_init(struct nvgpu_falcon *flcn) } if (flcn->is_falcon_supported) { - gk20a_falcon_engine_dependency_ops(flcn); + ga10b_falcon_engine_dependency_ops(flcn); } else { gk20a_falcon_sw_init(flcn); } diff --git a/drivers/gpu/nvgpu/common/gsp/gsp_bootstrap.c b/drivers/gpu/nvgpu/common/gsp/gsp_bootstrap.c new file mode 100644 index 000000000..4690fcfec --- /dev/null +++ b/drivers/gpu/nvgpu/common/gsp/gsp_bootstrap.c @@ -0,0 +1,251 @@ +/* + * Copyright (c) 2021, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#include +#include +#include +#include +#include +#include +#include +#include + +#include "gsp_priv.h" +#include "gsp_bootstrap.h" + +#define GSP_SIM_WAIT_TIME_MS 10000U +#define GSP_DBG_RISCV_FW_MANIFEST "sample-gsp.manifest.encrypt.bin.out.bin" +#define GSP_DBG_RISCV_FW_CODE "sample-gsp.text.encrypt.bin" +#define GSP_DBG_RISCV_FW_DATA "sample-gsp.data.encrypt.bin" + +static void gsp_release_firmware(struct gk20a *g, struct nvgpu_gsp *gsp) +{ + if (gsp->gsp_ucode.manifest != NULL) { + nvgpu_release_firmware(g, gsp->gsp_ucode.manifest); + } + + if (gsp->gsp_ucode.code != NULL) { + nvgpu_release_firmware(g, gsp->gsp_ucode.code); + } + + if (gsp->gsp_ucode.data != NULL) { + nvgpu_release_firmware(g, gsp->gsp_ucode.data); + } +} + +static int gsp_read_firmware(struct gk20a *g, struct gsp_fw *gsp_ucode) +{ + nvgpu_log_fn(g, " "); + + gsp_ucode->manifest = nvgpu_request_firmware(g, + GSP_DBG_RISCV_FW_MANIFEST, NVGPU_REQUEST_FIRMWARE_NO_WARN); + if (gsp_ucode->manifest == NULL) { + nvgpu_err(g, "GSP_DBG_RISCV_FW_MANIFEST ucode get failed"); + goto fw_release; + } + + gsp_ucode->code = nvgpu_request_firmware(g, + GSP_DBG_RISCV_FW_CODE, NVGPU_REQUEST_FIRMWARE_NO_WARN); + if (gsp_ucode->code == NULL) { + nvgpu_err(g, "GSP_DBG_RISCV_FW_CODE ucode get failed"); + goto fw_release; + } + + gsp_ucode->data = nvgpu_request_firmware(g, + GSP_DBG_RISCV_FW_DATA, NVGPU_REQUEST_FIRMWARE_NO_WARN); + if (gsp_ucode->data == NULL) { + nvgpu_err(g, "GSP_DBG_RISCV_FW_DATA ucode get failed"); + goto fw_release; + } + + return 0; + +fw_release: + gsp_release_firmware(g, g->gsp); + return -ENOENT; +} + +static int gsp_ucode_load_and_bootstrap(struct gk20a *g, + struct nvgpu_falcon *flcn, + struct gsp_fw *gsp_ucode) +{ + u32 dmem_size = 0U; + u32 code_size = gsp_ucode->code->size; + u32 data_size = gsp_ucode->data->size; + u32 manifest_size = gsp_ucode->manifest->size; + int err = 0; + + nvgpu_log_fn(g, " "); + + /* core reset */ + err = nvgpu_falcon_reset(flcn); + if (err != 0) { + nvgpu_err(g, "gsp core reset failed err=%d", err); + goto exit; + } + + g->ops.falcon.set_bcr(flcn); + err = nvgpu_falcon_get_mem_size(flcn, MEM_DMEM, &dmem_size); + if (err != 0) { + nvgpu_err(g, "gsp NVRISCV get DMEM size failed"); + goto exit; + } + + if ((data_size + manifest_size) > dmem_size) { + nvgpu_err(g, "gsp DMEM might overflow"); + err = -ENOMEM; + goto exit; + } + + err = nvgpu_falcon_copy_to_imem(flcn, 0x0, gsp_ucode->code->data, + code_size, 0, true, 0x0); + if (err != 0) { + nvgpu_err(g, "gsp NVRISCV code copy to IMEM failed"); + goto exit; + } + + err = nvgpu_falcon_copy_to_dmem(flcn, 0x0, gsp_ucode->data->data, + data_size, 0x0); + if (err != 0) { + nvgpu_err(g, "gsp NVRISCV data copy to DMEM failed"); + goto exit; + } + + err = nvgpu_falcon_copy_to_dmem(flcn, (dmem_size - manifest_size), + gsp_ucode->manifest->data, manifest_size, 0x0); + if (err != 0) { + nvgpu_err(g, "gsp NVRISCV manifest copy to DMEM failed"); + goto exit; + } + + /* + * Write zero value to mailbox-0 register which is updated by + * gsp ucode to denote its return status. + */ + nvgpu_falcon_mailbox_write(flcn, FALCON_MAILBOX_0, 0x0U); + + g->ops.falcon.bootstrap(flcn, 0x0); +exit: + return err; +} + +static int gsp_check_for_brom_completion(struct nvgpu_falcon *flcn, + signed int timeoutms) +{ + u32 reg = 0; + + nvgpu_log_fn(flcn->g, " "); + + do { + reg = flcn->g->ops.falcon.get_brom_retcode(flcn); + if (flcn->g->ops.falcon.check_brom_passed(reg)) { + break; + } + + if (timeoutms <= 0) { + nvgpu_err(flcn->g, "gsp BROM execution check timedout"); + goto exit; + } + + nvgpu_msleep(10); + timeoutms -= 10; + + } while (true); + + if ((reg & 0x3) == 0x2) { + nvgpu_err(flcn->g, "gsp BROM execution failed"); + goto exit; + } + + return 0; +exit: + flcn->g->ops.falcon.dump_brom_stats(flcn); + return -1; +} + +static int gsp_wait_for_mailbox_update(struct nvgpu_falcon *flcn, + u32 mailbox_index, signed int timeoutms) +{ + u32 mail_box_data = 0; + + nvgpu_log_fn(flcn->g, " "); + + do { + mail_box_data = flcn->g->ops.falcon.mailbox_read( + flcn, mailbox_index); + if (mail_box_data != 0U) { + nvgpu_info(flcn->g, + "gsp mailbox-0 updated successful with 0x%x", + mail_box_data); + break; + } + + if (timeoutms <= 0) { + nvgpu_err(flcn->g, "gsp mailbox check timedout"); + return -1; + } + + nvgpu_msleep(10); + timeoutms -= 10; + + } while (true); + + return 0; +} + +int gsp_bootstrap_ns(struct gk20a *g, struct nvgpu_gsp *gsp) +{ + int err = 0; + struct gsp_fw *gsp_ucode = &gsp->gsp_ucode; + + nvgpu_log_fn(g, " "); + + err = gsp_read_firmware(g, gsp_ucode); + if (err != 0) { + nvgpu_err(g, "gsp firmware reading failed"); + goto exit; + } + + err = gsp_ucode_load_and_bootstrap(g, gsp->gsp_flcn, gsp_ucode); + if (err != 0) { + nvgpu_err(g, "gsp load and bootstrap failed"); + goto exit; + } + + err = gsp_check_for_brom_completion(gsp->gsp_flcn, + GSP_SIM_WAIT_TIME_MS); + if (err != 0) { + nvgpu_err(g, "gsp BROM failed"); + goto exit; + } + + /* wait for mailbox-0 update with non-zero value */ + err = gsp_wait_for_mailbox_update(gsp->gsp_flcn, 0x0, + GSP_SIM_WAIT_TIME_MS); + if (err != 0) { + nvgpu_err(g, "gsp ucode failed to update mailbox-0"); + } + +exit: + gsp_release_firmware(g, g->gsp); + return err; +} diff --git a/drivers/gpu/nvgpu/common/gsp/gsp_bootstrap.h b/drivers/gpu/nvgpu/common/gsp/gsp_bootstrap.h new file mode 100644 index 000000000..95f65fd63 --- /dev/null +++ b/drivers/gpu/nvgpu/common/gsp/gsp_bootstrap.h @@ -0,0 +1,31 @@ +/* + * Copyright (c) 2021, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef NVGPU_GSP_BOOTSTRAP +#define NVGPU_GSP_BOOTSTRAP +struct nvgpu_gsp; + +#define GSP_UCODE_SIZE_MAX (256U * 1024U) + +int gsp_bootstrap_ns(struct gk20a *g, struct nvgpu_gsp *gsp); + +#endif /* NVGPU_GSP_BOOTSTRAP */ diff --git a/drivers/gpu/nvgpu/common/gsp/gsp_init.c b/drivers/gpu/nvgpu/common/gsp/gsp_init.c new file mode 100644 index 000000000..0b3184d1e --- /dev/null +++ b/drivers/gpu/nvgpu/common/gsp/gsp_init.c @@ -0,0 +1,85 @@ +/* + * Copyright (c) 2021, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#include +#include +#include +#include +#include + +#include "gsp_priv.h" +#include "gsp_bootstrap.h" + +void nvgpu_gsp_sw_deinit(struct gk20a *g) +{ + if (g->gsp != NULL) { + nvgpu_kfree(g, g->gsp); + g->gsp = NULL; + } +} + +int nvgpu_gsp_sw_init(struct gk20a *g) +{ + int err = 0; + + nvgpu_log_fn(g, " "); + + if (g->gsp != NULL) { + /* + * Recovery/unrailgate case, we do not need to do gsp init as + * gsp is set during cold boot & doesn't execute gsp clean up as + * part of power off sequence, so reuse to perform faster boot. + */ + return err; + } + + /* Init struct holding the gsp software state */ + g->gsp = (struct nvgpu_gsp *)nvgpu_kzalloc(g, sizeof(struct nvgpu_gsp)); + if (g->gsp == NULL) { + err = -ENOMEM; + goto exit; + } + + /* gsp falcon software state */ + g->gsp->gsp_flcn = &g->gsp_flcn; + +exit: + return err; +} + +int nvgpu_gsp_bootstrap(struct gk20a *g) +{ + int err = 0; + + nvgpu_log_fn(g, " "); + + err = gsp_bootstrap_ns(g, g->gsp); + if (err != 0) { + nvgpu_err(g, "GSP bootstrap failed"); + goto de_init; + } + + return err; +de_init: + nvgpu_gsp_sw_deinit(g); + return err; +} diff --git a/drivers/gpu/nvgpu/common/gsp/gsp_priv.h b/drivers/gpu/nvgpu/common/gsp/gsp_priv.h new file mode 100644 index 000000000..e054778ef --- /dev/null +++ b/drivers/gpu/nvgpu/common/gsp/gsp_priv.h @@ -0,0 +1,38 @@ +/* + * Copyright (c) 2021, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef NVGPU_GSP_PRIV +#define NVGPU_GSP_PRIV + +struct gsp_fw { + /* gsp ucode */ + struct nvgpu_firmware *code; + struct nvgpu_firmware *data; + struct nvgpu_firmware *manifest; +}; + +/* GSP descriptor's */ +struct nvgpu_gsp { + struct gsp_fw gsp_ucode; + struct nvgpu_falcon *gsp_flcn; +}; +#endif /* NVGPU_GSP_PRIV */ diff --git a/drivers/gpu/nvgpu/common/init/nvgpu_init.c b/drivers/gpu/nvgpu/common/init/nvgpu_init.c index e769ca026..50cc605da 100644 --- a/drivers/gpu/nvgpu/common/init/nvgpu_init.c +++ b/drivers/gpu/nvgpu/common/init/nvgpu_init.c @@ -40,6 +40,7 @@ #include #include #include +#include #include #include #include @@ -768,6 +769,10 @@ int nvgpu_finalize_poweron(struct gk20a *g) #ifdef CONFIG_NVGPU_DGPU NVGPU_INIT_TABLE_ENTRY(g->ops.sec2.init_sec2_setup_sw, NVGPU_SUPPORT_SEC2_RTOS), +#endif +#ifdef CONFIG_NVGPU_GSP_SCHEDULER + /* Init gsp ops */ + NVGPU_INIT_TABLE_ENTRY(&nvgpu_gsp_sw_init, NO_FLAG), #endif NVGPU_INIT_TABLE_ENTRY(g->ops.acr.acr_init, NVGPU_SEC_PRIVSECURITY), diff --git a/drivers/gpu/nvgpu/hal/gsp/gsp_ga10b.c b/drivers/gpu/nvgpu/hal/gsp/gsp_ga10b.c index 99bd0792f..35fd2dda1 100644 --- a/drivers/gpu/nvgpu/hal/gsp/gsp_ga10b.c +++ b/drivers/gpu/nvgpu/hal/gsp/gsp_ga10b.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2020, NVIDIA CORPORATION. All rights reserved. + * Copyright (c) 2021, NVIDIA CORPORATION. All rights reserved. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), @@ -40,3 +40,14 @@ u32 ga10b_gsp_falcon_base_addr(void) { return pgsp_falcon_irqsset_r(); } + +int ga10b_gsp_engine_reset(struct gk20a *g) +{ + gk20a_writel(g, pgsp_falcon_engine_r(), + pgsp_falcon_engine_reset_true_f()); + nvgpu_udelay(10); + gk20a_writel(g, pgsp_falcon_engine_r(), + pgsp_falcon_engine_reset_false_f()); + + return 0; +} diff --git a/drivers/gpu/nvgpu/hal/gsp/gsp_ga10b.h b/drivers/gpu/nvgpu/hal/gsp/gsp_ga10b.h index f61da19b1..77c919c28 100644 --- a/drivers/gpu/nvgpu/hal/gsp/gsp_ga10b.h +++ b/drivers/gpu/nvgpu/hal/gsp/gsp_ga10b.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2020, NVIDIA CORPORATION. All rights reserved. + * Copyright (c) 2021, NVIDIA CORPORATION. All rights reserved. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), @@ -25,5 +25,6 @@ u32 ga10b_gsp_falcon_base_addr(void); u32 ga10b_gsp_falcon2_base_addr(void); +int ga10b_gsp_engine_reset(struct gk20a *g); #endif /* GSP_GA10B_H */ diff --git a/drivers/gpu/nvgpu/hal/init/hal_ga10b.c b/drivers/gpu/nvgpu/hal/init/hal_ga10b.c index b1a7c80a9..cd4939382 100644 --- a/drivers/gpu/nvgpu/hal/init/hal_ga10b.c +++ b/drivers/gpu/nvgpu/hal/init/hal_ga10b.c @@ -1244,6 +1244,7 @@ static const struct gops_therm ga10b_ops_therm = { static const struct gops_gsp ga10b_ops_gsp = { .falcon_base_addr = ga10b_gsp_falcon_base_addr, .falcon2_base_addr = ga10b_gsp_falcon2_base_addr, + .gsp_reset = ga10b_gsp_engine_reset, }; static const struct gops_pmu ga10b_ops_pmu = { diff --git a/drivers/gpu/nvgpu/include/nvgpu/gk20a.h b/drivers/gpu/nvgpu/include/nvgpu/gk20a.h index efa365df0..f0d19d955 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/gk20a.h +++ b/drivers/gpu/nvgpu/include/nvgpu/gk20a.h @@ -108,6 +108,9 @@ struct vm_gk20a_mapping_batch; struct pmu_pg_stats_data; struct clk_domains_mon_status_params; struct nvgpu_cic_mon; +#ifdef CONFIG_NVGPU_GSP_SCHEDULER +struct nvgpu_gsp; +#endif enum nvgpu_flush_op; enum gk20a_mem_rw_flag; @@ -472,6 +475,10 @@ struct gk20a { struct nvgpu_pmu *pmu; /** Pointer to struct maintaining ACR unit's software state. */ struct nvgpu_acr *acr; +#ifdef CONFIG_NVGPU_GSP_SCHEDULER + /** Pointer to struct maintaining GSP unit's software state. */ + struct nvgpu_gsp *gsp; +#endif /** Top level struct maintaining ECC unit's software state. */ struct nvgpu_ecc ecc; /** @cond DOXYGEN_SHOULD_SKIP_THIS */ diff --git a/drivers/gpu/nvgpu/include/nvgpu/gsp.h b/drivers/gpu/nvgpu/include/nvgpu/gsp.h new file mode 100644 index 000000000..5ce1b2d6a --- /dev/null +++ b/drivers/gpu/nvgpu/include/nvgpu/gsp.h @@ -0,0 +1,30 @@ +/* + * Copyright (c) 2021, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef NVGPU_GSP +#define NVGPU_GSP +struct gk20a; + +int nvgpu_gsp_sw_init(struct gk20a *g); +int nvgpu_gsp_bootstrap(struct gk20a *g); +void nvgpu_gsp_sw_deinit(struct gk20a *g); +#endif /* NVGPU_GSP */ diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/ga10b/hw_pgsp_ga10b.h b/drivers/gpu/nvgpu/include/nvgpu/hw/ga10b/hw_pgsp_ga10b.h index 82486985b..d85a0a862 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/hw/ga10b/hw_pgsp_ga10b.h +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/ga10b/hw_pgsp_ga10b.h @@ -61,4 +61,7 @@ #define pgsp_falcon2_gsp_base_r() (0x00111000U) #define pgsp_falcon_irqsset_r() (0x00110000U) +#define pgsp_falcon_engine_r() (0x001103c0U) +#define pgsp_falcon_engine_reset_true_f() (0x1U) +#define pgsp_falcon_engine_reset_false_f() (0x0U) #endif diff --git a/drivers/gpu/nvgpu/os/linux/module.c b/drivers/gpu/nvgpu/os/linux/module.c index 1c5efb5b8..2756aaf89 100644 --- a/drivers/gpu/nvgpu/os/linux/module.c +++ b/drivers/gpu/nvgpu/os/linux/module.c @@ -83,6 +83,10 @@ #include "debug_pmgr.h" #include "dmabuf_priv.h" +#ifdef CONFIG_NVGPU_GSP_SCHEDULER +#include "nvgpu/gsp.h" +#endif + #ifdef CONFIG_NVGPU_SUPPORT_CDE #include "cde.h" #endif @@ -945,6 +949,10 @@ void gk20a_remove_support(struct gk20a *g) nvgpu_free_cyclestats_snapshot_data(g); #endif +#ifdef CONFIG_NVGPU_GSP_SCHEDULER + nvgpu_gsp_sw_deinit(g); +#endif + nvgpu_fbp_remove_support(g); nvgpu_remove_usermode_support(g);