diff --git a/arch/nvgpu-hal-new.yaml b/arch/nvgpu-hal-new.yaml index d77f4be84..c86cd8dde 100644 --- a/arch/nvgpu-hal-new.yaml +++ b/arch/nvgpu-hal-new.yaml @@ -145,7 +145,8 @@ clk_mon: owner: Ramesh M gpu: dgpu sources: [ hal/clk/clk_mon_tu104.c, - hal/clk/clk_mon_tu104.h ] + hal/clk/clk_mon_tu104.h, + include/nvgpu/clk_mon.h] clk_igpu: safe: no diff --git a/drivers/gpu/nvgpu/common/pmu/clk/clk.c b/drivers/gpu/nvgpu/common/pmu/clk/clk.c index 9acac7349..05a76db42 100644 --- a/drivers/gpu/nvgpu/common/pmu/clk/clk.c +++ b/drivers/gpu/nvgpu/common/pmu/clk/clk.c @@ -30,7 +30,6 @@ #include #include #include -#include #include "ucode_clk_inf.h" #include "clk_domain.h" diff --git a/drivers/gpu/nvgpu/common/pmu/perf/ucode_perf_change_seq_inf.h b/drivers/gpu/nvgpu/common/pmu/perf/ucode_perf_change_seq_inf.h index 8e349f2fa..e728fa5e2 100644 --- a/drivers/gpu/nvgpu/common/pmu/perf/ucode_perf_change_seq_inf.h +++ b/drivers/gpu/nvgpu/common/pmu/perf/ucode_perf_change_seq_inf.h @@ -40,6 +40,19 @@ #define CTRL_PERF_CHANGE_SEQ_SCRIPT_MAX_PROFILING_THREADS 8 #define CTRL_PERF_CHANGE_SEQ_SCRIPT_VF_SWITCH_MAX_STEPS 13U +struct ctrl_clk_domain_clk_mon_item { + u32 clk_api_domain; + u32 clk_freq_Mhz; + u32 low_threshold_percentage; + u32 high_threshold_percentage; +}; + +struct ctrl_clk_domain_clk_mon_list { + u8 num_domain; + struct ctrl_clk_domain_clk_mon_item + clk_domain[CTRL_CLK_CLK_DOMAIN_CLIENT_MAX_DOMAINS]; +}; + struct ctrl_volt_volt_rail_list_item { u8 rail_idx; u32 voltage_uv; diff --git a/drivers/gpu/nvgpu/hal/clk/clk_gk20a.h b/drivers/gpu/nvgpu/hal/clk/clk_gk20a.h index 9cb95715f..f0e56e5b3 100644 --- a/drivers/gpu/nvgpu/hal/clk/clk_gk20a.h +++ b/drivers/gpu/nvgpu/hal/clk/clk_gk20a.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2011 - 2019, NVIDIA CORPORATION. All rights reserved. + * Copyright (c) 2011 - 2020, NVIDIA CORPORATION. All rights reserved. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), @@ -90,6 +90,7 @@ struct pll_parms { }; struct namemap_cfg; +struct clk_domains_mon_status_params; struct clk_gk20a { struct gk20a *g; @@ -102,6 +103,7 @@ struct clk_gk20a { struct pll gpc_pll_last; struct nvgpu_mutex clk_mutex; struct namemap_cfg *clk_namemap; + struct clk_domains_mon_status_params *clk_mon_status; u32 namemap_num; u32 *namemap_xlat_table; bool sw_ready; diff --git a/drivers/gpu/nvgpu/hal/clk/clk_mon_tu104.c b/drivers/gpu/nvgpu/hal/clk/clk_mon_tu104.c index 55ae19319..39a036c82 100644 --- a/drivers/gpu/nvgpu/hal/clk/clk_mon_tu104.c +++ b/drivers/gpu/nvgpu/hal/clk/clk_mon_tu104.c @@ -25,9 +25,9 @@ #include #include #include -#include #include #include +#include #include #include "clk_mon_tu104.h" @@ -35,7 +35,7 @@ * Mapping between the clk domain and the various clock monitor registers * The rows represent clock domains starting from index 0 and column represent * the various registers each domain has, non available domains are set to 0 - * for easy accessing, refer nvgpu_pmu_clk_mon_init_domains() for valid domains. + * for easy accessing, refer nvgpu_clk_mon_init_domains() for valid domains. */ static u32 clock_mon_map_tu104[CLK_CLOCK_MON_DOMAIN_COUNT] [CLK_CLOCK_MON_REG_TYPE_COUNT] = { @@ -189,14 +189,32 @@ bool nvgpu_clk_mon_check_master_fault_status(struct gk20a *g) return false; } -int nvgpu_clk_mon_check_status(struct gk20a *g, - struct clk_domains_mon_status_params *clk_mon_status, - u32 domain_mask) +int nvgpu_clk_mon_alloc_memory(struct gk20a *g) +{ + struct clk_gk20a *clk = &g->clk; + + /* If already allocated, do not re-allocate */ + if (clk->clk_mon_status != NULL) { + return 0; + } + + clk->clk_mon_status = nvgpu_kzalloc(g, + sizeof(struct clk_domains_mon_status_params)); + if (clk->clk_mon_status == NULL) { + return -ENOMEM; + } + + return 0; +} + +int nvgpu_clk_mon_check_status(struct gk20a *g, u32 domain_mask) { u32 reg_address, bit_pos; u32 data; int status; + struct clk_domains_mon_status_params *clk_mon_status; + clk_mon_status = g->clk.clk_mon_status; clk_mon_status->clk_mon_domain_mask = domain_mask; /* * Parse through each domain and check for faults, each bit set @@ -277,3 +295,4 @@ bool nvgpu_clk_mon_check_pll_lock(struct gk20a *g) } return false; } + diff --git a/drivers/gpu/nvgpu/hal/clk/clk_mon_tu104.h b/drivers/gpu/nvgpu/hal/clk/clk_mon_tu104.h index fd7172227..271d1786e 100644 --- a/drivers/gpu/nvgpu/hal/clk/clk_mon_tu104.h +++ b/drivers/gpu/nvgpu/hal/clk/clk_mon_tu104.h @@ -31,11 +31,27 @@ #define FMON_FAULT_STATUS_PRIV_MASK 0x3U #define CLK_CLOCK_MON_REG_TYPE_COUNT 0x4U #define CLK_MON_BITS_PER_BYTE 0x8U +/* + * The Maximum count of clock domains supported + */ +#define CLK_CLOCK_MON_DOMAIN_COUNT 0x32U + + +struct clk_domain_mon_status { + u32 clk_api_domain; + u32 low_threshold; + u32 high_threshold; + u32 clk_domain_fault_status; +}; + +struct clk_domains_mon_status_params { + u32 clk_mon_domain_mask; + struct clk_domain_mon_status + clk_mon_list[CLK_CLOCK_MON_DOMAIN_COUNT]; +}; bool nvgpu_clk_mon_check_master_fault_status(struct gk20a *g); -int nvgpu_clk_mon_check_status(struct gk20a *g, struct - clk_domains_mon_status_params *clk_mon_status, - u32 domain_mask); +int nvgpu_clk_mon_check_status(struct gk20a *g, u32 domain_mask); bool nvgpu_clk_mon_check_clk_good(struct gk20a *g); bool nvgpu_clk_mon_check_pll_lock(struct gk20a *g); #endif /* CLK_MON_TU104_H */ diff --git a/drivers/gpu/nvgpu/hal/init/hal_tu104.c b/drivers/gpu/nvgpu/hal/init/hal_tu104.c index 546b1ad2d..953eed8a1 100644 --- a/drivers/gpu/nvgpu/hal/init/hal_tu104.c +++ b/drivers/gpu/nvgpu/hal/init/hal_tu104.c @@ -237,6 +237,7 @@ #include #include #include +#include #include @@ -1304,13 +1305,18 @@ static const struct gpu_ops tu104_ops = { .get_change_seq_time = tu104_get_change_seq_time, #endif .change_host_clk_source = tu104_change_host_clk_source, - .clk_mon_check_master_fault_status = - nvgpu_clk_mon_check_master_fault_status, - .clk_mon_check_status = nvgpu_clk_mon_check_status, + .perf_pmu_vfe_load = nvgpu_pmu_perf_load, .clk_mon_init_domains = nvgpu_pmu_clk_mon_init_domains, + + }, + .clk_mon = { + .clk_mon_alloc_memory = nvgpu_clk_mon_alloc_memory, + .clk_mon_check_master_fault_status = + nvgpu_clk_mon_check_master_fault_status, + .clk_mon_check_status = nvgpu_clk_mon_check_status, .clk_mon_check_clk_good = nvgpu_clk_mon_check_clk_good, .clk_mon_check_pll_lock = nvgpu_clk_mon_check_pll_lock, - .perf_pmu_vfe_load = nvgpu_pmu_perf_load, + }, #ifdef CONFIG_NVGPU_CLK_ARB .clk_arb = { @@ -1688,6 +1694,7 @@ int tu104_init_hal(struct gk20a *g) gops->clk.get_crystal_clk_hz = tu104_ops.clk.get_crystal_clk_hz; gops->clk.measure_freq = tu104_ops.clk.measure_freq; gops->clk.suspend_clk_support = tu104_ops.clk.suspend_clk_support; + gops->clk_mon = tu104_ops.clk_mon; #ifdef CONFIG_NVGPU_CLK_ARB gops->clk_arb = tu104_ops.clk_arb; #endif diff --git a/drivers/gpu/nvgpu/include/nvgpu/clk_mon.h b/drivers/gpu/nvgpu/include/nvgpu/clk_mon.h new file mode 100644 index 000000000..eeb064449 --- /dev/null +++ b/drivers/gpu/nvgpu/include/nvgpu/clk_mon.h @@ -0,0 +1,27 @@ +/* + * Copyright (c) 2020, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ +#ifndef CLK_MON_H +#define CLK_MON_H + +int nvgpu_clk_mon_alloc_memory(struct gk20a *g); + +#endif /* CLK_MON_H */ diff --git a/drivers/gpu/nvgpu/include/nvgpu/gk20a.h b/drivers/gpu/nvgpu/include/nvgpu/gk20a.h index afdfc5ccd..7af551f2b 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/gk20a.h +++ b/drivers/gpu/nvgpu/include/nvgpu/gk20a.h @@ -364,22 +364,24 @@ struct gpu_ops { int (*mclk_change)(struct gk20a *g, u16 val); void (*get_change_seq_time)(struct gk20a *g, s64 *change_time); void (*change_host_clk_source)(struct gk20a *g); + u32 (*clk_mon_init_domains)(struct gk20a *g); bool split_rail_support; bool support_pmgr_domain; bool support_lpwr_pg; int (*perf_pmu_vfe_load)(struct gk20a *g); bool support_vf_point; u8 lut_num_entries; + } clk; +#ifdef CONFIG_NVGPU_DGPU + struct { + int (*clk_mon_alloc_memory)(struct gk20a *g); bool (*clk_mon_check_master_fault_status)(struct gk20a *g); int (*clk_mon_check_status)(struct gk20a *g, - struct clk_domains_mon_status_params *clk_mon_status, u32 domain_mask); - u32 (*clk_mon_init_domains)(struct gk20a *g); -#ifdef CONFIG_NVGPU_DGPU bool (*clk_mon_check_clk_good)(struct gk20a *g); bool (*clk_mon_check_pll_lock)(struct gk20a *g); + } clk_mon; #endif - } clk; #ifdef CONFIG_NVGPU_CLK_ARB struct { int (*clk_arb_init_arbiter)(struct gk20a *g); diff --git a/drivers/gpu/nvgpu/include/nvgpu/pmu/clk/clk.h b/drivers/gpu/nvgpu/include/nvgpu/pmu/clk/clk.h index f4cb1c6b0..5404b3210 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/pmu/clk/clk.h +++ b/drivers/gpu/nvgpu/include/nvgpu/pmu/clk/clk.h @@ -106,14 +106,11 @@ #define CTRL_CLK_LUT_NUM_ENTRIES_MAX 128U #define CTRL_CLK_LUT_NUM_ENTRIES_GV10x 128U #define CTRL_CLK_LUT_NUM_ENTRIES_GP10x 100U + /* * The Minimum resolution of frequency which is supported */ #define FREQ_STEP_SIZE_MHZ 15U -/* - * The Maximum count of clock domains supported - */ -#define CLK_CLOCK_MON_DOMAIN_COUNT 0x32U struct gk20a; struct clk_avfs_fll_objs; @@ -128,33 +125,6 @@ struct nvgpu_clk_domain; struct nvgpu_clk_arb; struct nvgpu_clk_pmupstate; - -struct clk_domain_mon_status { - u32 clk_api_domain; - u32 low_threshold; - u32 high_threshold; - u32 clk_domain_fault_status; -}; - -struct clk_domains_mon_status_params { - u32 clk_mon_domain_mask; - struct clk_domain_mon_status - clk_mon_list[CLK_CLOCK_MON_DOMAIN_COUNT]; -}; - -struct ctrl_clk_domain_clk_mon_item { - u32 clk_api_domain; - u32 clk_freq_Mhz; - u32 low_threshold_percentage; - u32 high_threshold_percentage; -}; - -struct ctrl_clk_domain_clk_mon_list { - u8 num_domain; - struct ctrl_clk_domain_clk_mon_item - clk_domain[CTRL_CLK_CLK_DOMAIN_CLIENT_MAX_DOMAINS]; -}; - struct ctrl_clk_clk_domain_list_item_v1 { u32 clk_domain; u32 clk_freq_khz; @@ -181,7 +151,6 @@ int clk_get_fll_clks_per_clk_domain(struct gk20a *g, int nvgpu_pmu_clk_domain_freq_to_volt(struct gk20a *g, u8 clkdomain_idx, u32 *pclkmhz, u32 *pvoltuv, u8 railidx); int nvgpu_pmu_clk_domain_get_from_index(struct gk20a *g, u32 *domain, u32 index); -u32 nvgpu_pmu_clk_mon_init_domains(struct gk20a *g); int nvgpu_pmu_clk_pmu_setup(struct gk20a *g); int nvgpu_pmu_clk_sw_setup(struct gk20a *g); int nvgpu_pmu_clk_init(struct gk20a *g); @@ -204,4 +173,5 @@ void clk_set_p0_clk_per_domain(struct gk20a *g, u8 *gpcclk_domain, u32 *gpcclk_clkmhz, struct nvgpu_clk_slave_freq *vf_point, struct nvgpu_pmu_perf_change_input_clk_info *change_input); +u32 nvgpu_pmu_clk_mon_init_domains(struct gk20a *g); #endif /* NVGPU_PMU_CLK_H */