diff --git a/drivers/gpu/nvgpu/include/nvgpu/vgpu/tegra_vgpu.h b/drivers/gpu/nvgpu/include/nvgpu/vgpu/tegra_vgpu.h
index c8af4b80d..83dd17db5 100644
--- a/drivers/gpu/nvgpu/include/nvgpu/vgpu/tegra_vgpu.h
+++ b/drivers/gpu/nvgpu/include/nvgpu/vgpu/tegra_vgpu.h
@@ -87,7 +87,6 @@ enum {
 	TEGRA_VGPU_CMD_CHANNEL_FREE_HWPM_CTX = 47,
 	TEGRA_VGPU_CMD_GR_CTX_ALLOC = 48,
 	TEGRA_VGPU_CMD_GR_CTX_FREE = 49,
-	TEGRA_VGPU_CMD_CHANNEL_BIND_GR_CTX = 50,
 	TEGRA_VGPU_CMD_TSG_BIND_GR_CTX = 51,
 	TEGRA_VGPU_CMD_TSG_BIND_CHANNEL = 52,
 	TEGRA_VGPU_CMD_TSG_UNBIND_CHANNEL = 53,
@@ -404,11 +403,6 @@ struct tegra_vgpu_gr_ctx_params {
 	u32 tsg_id;
 };
 
-struct tegra_vgpu_channel_bind_gr_ctx_params {
-	u64 ch_handle;
-	u64 gr_ctx_handle;
-};
-
 struct tegra_vgpu_tsg_bind_gr_ctx_params {
 	u32 tsg_id;
 	u64 gr_ctx_handle;
@@ -661,7 +655,6 @@ struct tegra_vgpu_cmd_msg {
 		struct tegra_vgpu_channel_set_ctxsw_mode set_ctxsw_mode;
 		struct tegra_vgpu_channel_free_hwpm_ctx free_hwpm_ctx;
 		struct tegra_vgpu_gr_ctx_params gr_ctx;
-		struct tegra_vgpu_channel_bind_gr_ctx_params ch_bind_gr_ctx;
 		struct tegra_vgpu_tsg_bind_gr_ctx_params tsg_bind_gr_ctx;
 		struct tegra_vgpu_tsg_bind_unbind_channel_params tsg_bind_unbind_channel;
 		struct tegra_vgpu_tsg_open_rel_params tsg_open;
diff --git a/drivers/gpu/nvgpu/vgpu/gr_vgpu.c b/drivers/gpu/nvgpu/vgpu/gr_vgpu.c
index 5cc907c33..8b6ce1ed0 100644
--- a/drivers/gpu/nvgpu/vgpu/gr_vgpu.c
+++ b/drivers/gpu/nvgpu/vgpu/gr_vgpu.c
@@ -450,32 +450,6 @@ void vgpu_gr_free_gr_ctx(struct gk20a *g,
 	}
 }
 
-static int vgpu_gr_ch_bind_gr_ctx(struct channel_gk20a *c)
-{
-	struct tsg_gk20a *tsg;
-	struct nvgpu_gr_ctx *gr_ctx;
-	struct tegra_vgpu_cmd_msg msg = {0};
-	struct tegra_vgpu_channel_bind_gr_ctx_params *p =
-				&msg.params.ch_bind_gr_ctx;
-	int err;
-
-	tsg = tsg_gk20a_from_ch(c);
-	if (!tsg)
-		return -EINVAL;
-
-	gr_ctx = tsg->gr_ctx;
-
-	msg.cmd = TEGRA_VGPU_CMD_CHANNEL_BIND_GR_CTX;
-	msg.handle = vgpu_get_handle(c->g);
-	p->ch_handle = c->virt_ctx;
-	p->gr_ctx_handle = gr_ctx->virt_ctx;
-	err = vgpu_comm_sendrecv(&msg, sizeof(msg), sizeof(msg));
-	err = err ? err : msg.ret;
-	WARN_ON(err);
-
-	return err;
-}
-
 static int vgpu_gr_tsg_bind_gr_ctx(struct tsg_gk20a *tsg)
 {
 	struct nvgpu_gr_ctx *gr_ctx = tsg->gr_ctx;
@@ -543,12 +517,6 @@ int vgpu_gr_alloc_obj_ctx(struct channel_gk20a  *c, u32 class_num, u32 flags)
 			goto out;
 		}
 
-		err = vgpu_gr_ch_bind_gr_ctx(c);
-		if (err) {
-			nvgpu_err(g, "fail to bind gr ctx buffer");
-			goto out;
-		}
-
 		/* allocate patch buffer */
 		err = vgpu_gr_alloc_channel_patch_ctx(g, c);
 		if (err) {
@@ -589,12 +557,6 @@ int vgpu_gr_alloc_obj_ctx(struct channel_gk20a  *c, u32 class_num, u32 flags)
 			goto out;
 		}
 	} else {
-		err = vgpu_gr_ch_bind_gr_ctx(c);
-		if (err) {
-			nvgpu_err(g, "fail to bind gr ctx buffer");
-			goto out;
-		}
-
 		/* commit gr ctx buffer */
 		err = g->ops.gr.commit_inst(c, gr_ctx->mem.gpu_va);
 		if (err) {