nv-tegra-mirror/linux-nvgpu
1
0
Fork 0
mirror of git://nv-tegra.nvidia.com/linux-nvgpu.git synced 2025-12-22 17:36:20 +03:00
Code Issues Packages Projects Releases Wiki Activity

gpu: nvgpu: address priv_ring unit code inspection gaps

Browse Source 
1. Hardcoded constants are defined using #define are converted to
   const.
2. set_ppriv_timeout_settings HAL is not applicable from gm20b.
   Hence remove it completely.

JIRA NVGPU-6903

Change-Id: Ic096c5dc87aa45db0aa05482947cd032ae72bdd4
Signed-off-by: Sagar Kamble <skamble@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2552581
(cherry picked from commit c5fb38a54208330f24754fed33d7242903dbac59)
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2623635
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
This commit is contained in:
Sagar Kamble
2021-07-01 18:09:29 +05:30
committed by mobile promotions
parent 48cd58d332
commit d3b417ce2c
19 changed files with 13 additions and 113 deletions
Download Patch File Download Diff File Expand all files Collapse all files

4
drivers/gpu/nvgpu/common/gr/gr.c
View File

@@ -239,10 +239,6 @@ static int gr_init_setup_hw(struct gk20a *g, struct nvgpu_gr *gr)
g->ops.gr.init.pes_vsc_stream(g);
}
if (g->ops.priv_ring.set_ppriv_timeout_settings != NULL) {
g->ops.priv_ring.set_ppriv_timeout_settings(g);
}
/** Enable fecs error interrupts */
g->ops.gr.falcon.fecs_host_int_enable(g);
g->ops.gr.intr.enable_hww_exceptions(g);

1
drivers/gpu/nvgpu/hal/init/hal_ga100.c
View File

@@ -1639,7 +1639,6 @@ static const struct gops_priv_ring ga100_ops_priv_ring = {
.isr_handle_0 = ga10b_priv_ring_isr_handle_0,
.isr_handle_1 = ga10b_priv_ring_isr_handle_1,
.decode_error_code = ga10b_priv_ring_decode_error_code,
.set_ppriv_timeout_settings = NULL,
.enum_ltc = ga10b_priv_ring_enum_ltc,
.get_gpc_count = gm20b_priv_ring_get_gpc_count,
.get_fbp_count = gm20b_priv_ring_get_fbp_count,

1
drivers/gpu/nvgpu/hal/init/hal_ga10b.c
View File

@@ -1644,7 +1644,6 @@ static const struct gops_priv_ring ga10b_ops_priv_ring = {
.isr_handle_0 = ga10b_priv_ring_isr_handle_0,
.isr_handle_1 = ga10b_priv_ring_isr_handle_1,
.decode_error_code = ga10b_priv_ring_decode_error_code,
.set_ppriv_timeout_settings = NULL,
.enum_ltc = ga10b_priv_ring_enum_ltc,
.get_gpc_count = gm20b_priv_ring_get_gpc_count,
.get_fbp_count = gm20b_priv_ring_get_fbp_count,

1
drivers/gpu/nvgpu/hal/init/hal_gm20b.c
View File

@@ -1032,7 +1032,6 @@ static const struct gops_falcon gm20b_ops_falcon = {
static const struct gops_priv_ring gm20b_ops_priv_ring = {
.enable_priv_ring = gm20b_priv_ring_enable,
.isr = gm20b_priv_ring_isr,
.set_ppriv_timeout_settings = gm20b_priv_set_timeout_settings,
.enum_ltc = gm20b_priv_ring_enum_ltc,
.get_gpc_count = gm20b_priv_ring_get_gpc_count,
.get_fbp_count = gm20b_priv_ring_get_fbp_count,

1
drivers/gpu/nvgpu/hal/init/hal_gv11b.c
View File

@@ -1421,7 +1421,6 @@ static const struct gops_priv_ring gv11b_ops_priv_ring = {
.isr_handle_0 = gp10b_priv_ring_isr_handle_0,
.isr_handle_1 = gp10b_priv_ring_isr_handle_1,
.decode_error_code = gp10b_priv_ring_decode_error_code,
.set_ppriv_timeout_settings = gm20b_priv_set_timeout_settings,
.enum_ltc = gm20b_priv_ring_enum_ltc,
.get_gpc_count = gm20b_priv_ring_get_gpc_count,
.get_fbp_count = gm20b_priv_ring_get_fbp_count,

1
drivers/gpu/nvgpu/hal/init/hal_tu104.c
View File

@@ -1516,7 +1516,6 @@ static const struct gops_priv_ring tu104_ops_priv_ring = {
.isr_handle_0 = gp10b_priv_ring_isr_handle_0,
.isr_handle_1 = gp10b_priv_ring_isr_handle_1,
.decode_error_code = gp10b_priv_ring_decode_error_code,
.set_ppriv_timeout_settings = NULL,
.enum_ltc = gm20b_priv_ring_enum_ltc,
.get_gpc_count = gm20b_priv_ring_get_gpc_count,
.get_fbp_count = gm20b_priv_ring_get_fbp_count,

3
drivers/gpu/nvgpu/hal/priv_ring/priv_ring_gm20b.h
View File

@@ -1,5 +1,5 @@
/*
* Copyright (c) 2011-2021, NVIDIA CORPORATION. All rights reserved.
* Copyright (c) 2011-2022, NVIDIA CORPORATION. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
@@ -54,7 +54,6 @@ struct gk20a;
void gm20b_priv_ring_isr(struct gk20a *g);
#endif
int gm20b_priv_ring_enable(struct gk20a *g);
void gm20b_priv_set_timeout_settings(struct gk20a *g);
u32 gm20b_priv_ring_enum_ltc(struct gk20a *g);
u32 gm20b_priv_ring_get_gpc_count(struct gk20a *g);

12
drivers/gpu/nvgpu/hal/priv_ring/priv_ring_gm20b_fusa.c
View File

@@ -1,7 +1,7 @@
/*
* GM20B priv ring
*
* Copyright (c) 2011-2021, NVIDIA CORPORATION. All rights reserved.
* Copyright (c) 2011-2022, NVIDIA CORPORATION. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
@@ -95,16 +95,6 @@ int gm20b_priv_ring_enable(struct gk20a *g)
return 0;
}
void gm20b_priv_set_timeout_settings(struct gk20a *g)
{
/*
* Bug 1340570: increase the clock timeout to avoid potential
* operation failure at high gpcclk rate. Default values are 0x400.
*/
nvgpu_writel(g, pri_ringstation_sys_master_config_r(0x15), 0x800);
nvgpu_writel(g, pri_ringstation_gpc_master_config_r(0xa), 0x800);
}
u32 gm20b_priv_ring_enum_ltc(struct gk20a *g)
{
return nvgpu_readl(g, pri_ringmaster_enum_ltc_r());

5
drivers/gpu/nvgpu/hal/priv_ring/priv_ring_gp10b.h
View File

@@ -1,7 +1,7 @@
/*
* GP10B PRIV ringmaster
*
* Copyright (c) 2011-2020, NVIDIA CORPORATION. All rights reserved.
* Copyright (c) 2011-2022, NVIDIA CORPORATION. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
@@ -26,9 +26,6 @@
struct gk20a;
#define GP10B_PRIV_RING_POLL_CLEAR_INTR_RETRIES 100
#define GP10B_PRIV_RING_POLL_CLEAR_INTR_UDELAY 20
void gp10b_priv_ring_isr(struct gk20a *g);
void gp10b_priv_ring_decode_error_code(struct gk20a *g, u32 error_code);
void gp10b_priv_ring_isr_handle_0(struct gk20a *g, u32 status0);

14
drivers/gpu/nvgpu/hal/priv_ring/priv_ring_gp10b_fusa.c
View File

@@ -37,6 +37,9 @@
#include "priv_ring_gp10b.h"
static const u32 poll_retries = 100;
static const u32 poll_delay = 20;
static const char *const error_type_badf1xyy[] = {
"client timeout",
"decode error",
@@ -204,9 +207,9 @@ void gp10b_priv_ring_isr_handle_1(struct gk20a *g, u32 status1)
void gp10b_priv_ring_isr(struct gk20a *g)
{
u32 retries = poll_retries;
u32 status0, status1;
u32 cmd;
s32 retry;
status0 = nvgpu_readl(g, pri_ringmaster_intr_status0_r());
status1 = nvgpu_readl(g, pri_ringmaster_intr_status1_r());
@@ -224,18 +227,17 @@ void gp10b_priv_ring_isr(struct gk20a *g)
nvgpu_writel(g, pri_ringmaster_command_r(), cmd);
/* poll for clear interrupt done */
retry = GP10B_PRIV_RING_POLL_CLEAR_INTR_RETRIES;
cmd = pri_ringmaster_command_cmd_v(
nvgpu_readl(g, pri_ringmaster_command_r()));
while ((cmd != pri_ringmaster_command_cmd_no_cmd_v()) && (retry != 0)) {
nvgpu_udelay(GP10B_PRIV_RING_POLL_CLEAR_INTR_UDELAY);
while ((cmd != pri_ringmaster_command_cmd_no_cmd_v()) && (retries != 0U)) {
nvgpu_udelay(poll_delay);
cmd = pri_ringmaster_command_cmd_v(
nvgpu_readl(g, pri_ringmaster_command_r()));
retry--;
retries--;
}
if (retry == 0) {
if (retries == 0U) {
nvgpu_err(g, "priv ringmaster intr ack failed");
}
}

1
drivers/gpu/nvgpu/hal/vgpu/init/vgpu_hal_ga10b.c
View File

@@ -1026,7 +1026,6 @@ static const struct gops_falcon vgpu_ga10b_ops_falcon = {
static const struct gops_priv_ring vgpu_ga10b_ops_priv_ring = {
.enable_priv_ring = NULL,
.isr = NULL,
.set_ppriv_timeout_settings = NULL,
.enum_ltc = NULL,
.get_gpc_count = vgpu_gr_get_gpc_count,
};

1
drivers/gpu/nvgpu/hal/vgpu/init/vgpu_hal_gv11b.c
View File

@@ -996,7 +996,6 @@ static const struct gops_falcon vgpu_gv11b_ops_falcon = {
static const struct gops_priv_ring vgpu_gv11b_ops_priv_ring = {
.enable_priv_ring = NULL,
.isr = NULL,
.set_ppriv_timeout_settings = NULL,
.enum_ltc = NULL,
.get_gpc_count = vgpu_gr_get_gpc_count,
};

19
drivers/gpu/nvgpu/include/nvgpu/gops/priv_ring.h
View File

@@ -167,25 +167,6 @@ struct gops_priv_ring {
void (*isr_handle_1)(struct gk20a *g, u32 status1);
/**
* @brief Sets Priv ring timeout value in cycles.
* @brief Sets Priv ring timeout value in cycles when initializing GR H/W unit.
*
* @param g [in] Pointer to GPU driver struct.
* - The function does not perform validation of g parameter.
*
* This functions sets h/w specified timeout value in the number of
* cycles after sending a priv request. If timeout is exceeded then
* timeout error is reported back via \ref #isr_stall "g->ops.mc.isr_stall(g)".
*
* Steps:
* - Write \a 0x800 to register pri_ringstation_sys_master_config_r()
* at offset 0x15.
* - Write \a 0x800 to register pri_ringstation_gpc_master_config_r()
* at offset 0xa.
*/
void (*set_ppriv_timeout_settings)(struct gk20a *g);
/**
* @brief Returns number of enumerated Level Two Cache (LTC) chiplets.
*