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gpu: nvgpu: address priv_ring unit code inspection gaps

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1. Hardcoded constants are defined using #define are converted to
   const.
2. set_ppriv_timeout_settings HAL is not applicable from gm20b.
   Hence remove it completely.

JIRA NVGPU-6903

Change-Id: Ic096c5dc87aa45db0aa05482947cd032ae72bdd4
Signed-off-by: Sagar Kamble <skamble@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2552581
(cherry picked from commit c5fb38a54208330f24754fed33d7242903dbac59)
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2623635
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
This commit is contained in:
Sagar Kamble
2021-07-01 18:09:29 +05:30
committed by mobile promotions
parent 48cd58d332
commit d3b417ce2c
19 changed files with 13 additions and 113 deletions
Download Patch File Download Diff File Expand all files Collapse all files

1
userspace/required_tests.ini
View File

@@ -996,7 +996,6 @@ test_get_gpc_count.priv_ring_get_gpc_count=0
test_priv_ring_free_reg_space.priv_ring_free_reg_space=0
test_priv_ring_isr.priv_ring_isr=0
test_priv_ring_setup.priv_ring_setup=0
test_set_ppriv_timeout_settings.priv_ring_set_ppriv_timeout_settings=0
[ptimer]
ptimer_test_free_env.ptimer_free_env=0

5
userspace/units/gr/init/nvgpu-gr-init.c
View File

@@ -1,5 +1,5 @@
/*
* Copyright (c) 2019-2020, NVIDIA CORPORATION. All rights reserved.
* Copyright (c) 2019-2022, NVIDIA CORPORATION. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
@@ -355,7 +355,6 @@ static int test_gr_init_setup_hw_error(struct gk20a *g)
{
int err;
g->ops.priv_ring.set_ppriv_timeout_settings = NULL;
g->ops.gr.init.ecc_scrub_reg = NULL;
err = nvgpu_gr_init_support(g);
if (err != 0) {
@@ -369,8 +368,6 @@ static int test_gr_init_setup_hw_error(struct gk20a *g)
if (err == 0) {
return UNIT_FAIL;
}
g->ops.priv_ring.set_ppriv_timeout_settings =
gr_init_gops.priv_ring.set_ppriv_timeout_settings;
g->ops.gr.init.ecc_scrub_reg =
gr_init_gops.gr.init.ecc_scrub_reg;

29
userspace/units/priv_ring/nvgpu-priv_ring.c
View File

@@ -118,8 +118,6 @@ int test_priv_ring_setup(struct unit_module *m, struct gk20a *g, void *args)
g->ops.priv_ring.isr_handle_0 = gp10b_priv_ring_isr_handle_0;
g->ops.priv_ring.isr_handle_1 = gp10b_priv_ring_isr_handle_1;
g->ops.priv_ring.decode_error_code = gp10b_priv_ring_decode_error_code;
g->ops.priv_ring.set_ppriv_timeout_settings =
gm20b_priv_set_timeout_settings;
g->ops.priv_ring.enum_ltc = gm20b_priv_ring_enum_ltc;
g->ops.priv_ring.get_gpc_count = gm20b_priv_ring_get_gpc_count;
g->ops.priv_ring.get_fbp_count = gm20b_priv_ring_get_fbp_count;
@@ -255,31 +253,6 @@ end:
return ret;
}
int test_set_ppriv_timeout_settings(struct unit_module *m, struct gk20a *g,
void *args)
{
int ret = UNIT_SUCCESS;
u32 val_sys;
u32 val_gpc;
/* Call set_ppriv_timeout_settings HAL to set the timeout values
* to 0x800.
*/
g->ops.priv_ring.set_ppriv_timeout_settings(g);
/* Read back the registers to make sure the timeouts are set to 0x800 */
val_sys = nvgpu_posix_io_readl_reg_space(g,
pri_ringstation_sys_master_config_r(0x15));
val_gpc = nvgpu_posix_io_readl_reg_space(g,
pri_ringstation_gpc_master_config_r(0xa));
if ((val_sys != 0x800) || (val_gpc != 0x800)) {
unit_err(m, "Timeout setting failed.\n");
ret = UNIT_FAIL;
}
return ret;
}
int test_enum_ltc(struct unit_module *m, struct gk20a *g, void *args)
{
int ret = UNIT_SUCCESS;
@@ -413,8 +386,6 @@ int test_decode_error_code(struct unit_module *m, struct gk20a *g, void *args)
struct unit_module_test priv_ring_tests[] = {
UNIT_TEST(priv_ring_setup, test_priv_ring_setup, NULL, 0),
UNIT_TEST(priv_ring_enable_priv_ring, test_enable_priv_ring, NULL, 0),
UNIT_TEST(priv_ring_set_ppriv_timeout_settings,
test_set_ppriv_timeout_settings, NULL, 0),
UNIT_TEST(priv_ring_enum_ltc, test_enum_ltc, NULL, 0),
UNIT_TEST(priv_ring_get_gpc_count, test_get_gpc_count, NULL, 0),
UNIT_TEST(priv_ring_get_fbp_count, test_get_fbp_count, NULL, 0),

25
userspace/units/priv_ring/nvgpu-priv_ring.h
View File

@@ -1,5 +1,5 @@
/*
* Copyright (c) 2019-2021, NVIDIA CORPORATION. All rights reserved.
* Copyright (c) 2019-2022, NVIDIA CORPORATION. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
@@ -93,29 +93,6 @@ int test_priv_ring_free_reg_space(struct unit_module *m, struct gk20a *g, void *
*/
int test_enable_priv_ring(struct unit_module *m, struct gk20a *g, void *args);
/**
* Test specification for: test_set_ppriv_timeout_settings
*
* Description: Verify the priv_ring.set_ppriv_timeout_settings HAL.
*
* Test Type: Feature
*
* Targets: gops_priv_ring.set_ppriv_timeout_settings,
* gm20b_priv_set_timeout_settings
*
* Input: test_priv_ring_setup() has been executed.
*
* Steps:
* - Call set_ppriv_timeout_settings HAL to set the timeout values to 0x800.
* - Read back the registers to make sure the timeouts are set to 0x800.
*
* Output:
* - UNIT_FAIL if above HAL fails to set timeouts.
* - UNIT_SUCCESS otherwise.
*/
int test_set_ppriv_timeout_settings(struct unit_module *m, struct gk20a *g,
void *args);
/**
* Test specification for: test_enum_ltc
*