gpu: nvgpu: address priv_ring unit code inspection gaps

1. Hardcoded constants are defined using #define are converted to
   const.
2. set_ppriv_timeout_settings HAL is not applicable from gm20b.
   Hence remove it completely.

JIRA NVGPU-6903

Change-Id: Ic096c5dc87aa45db0aa05482947cd032ae72bdd4
Signed-off-by: Sagar Kamble <skamble@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2552581
(cherry picked from commit c5fb38a54208330f24754fed33d7242903dbac59)
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2623635
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>

drivers/gpu/nvgpu/common/gr/gr.c

@@ -239,10 +239,6 @@ static int gr_init_setup_hw(struct gk20a *g, struct nvgpu_gr *gr)
 		g->ops.gr.init.pes_vsc_stream(g);
 	}
 
-	if (g->ops.priv_ring.set_ppriv_timeout_settings != NULL) {
-		g->ops.priv_ring.set_ppriv_timeout_settings(g);
-	}
-
 	/** Enable fecs error interrupts */
 	g->ops.gr.falcon.fecs_host_int_enable(g);
 	g->ops.gr.intr.enable_hww_exceptions(g);

drivers/gpu/nvgpu/hal/init/hal_ga100.c

@@ -1639,7 +1639,6 @@ static const struct gops_priv_ring ga100_ops_priv_ring = {
 	.isr_handle_0 = ga10b_priv_ring_isr_handle_0,
 	.isr_handle_1 = ga10b_priv_ring_isr_handle_1,
 	.decode_error_code = ga10b_priv_ring_decode_error_code,
-	.set_ppriv_timeout_settings = NULL,
 	.enum_ltc = ga10b_priv_ring_enum_ltc,
 	.get_gpc_count = gm20b_priv_ring_get_gpc_count,
 	.get_fbp_count = gm20b_priv_ring_get_fbp_count,

drivers/gpu/nvgpu/hal/init/hal_ga10b.c

@@ -1644,7 +1644,6 @@ static const struct gops_priv_ring ga10b_ops_priv_ring = {
 	.isr_handle_0 = ga10b_priv_ring_isr_handle_0,
 	.isr_handle_1 = ga10b_priv_ring_isr_handle_1,
 	.decode_error_code = ga10b_priv_ring_decode_error_code,
-	.set_ppriv_timeout_settings = NULL,
 	.enum_ltc = ga10b_priv_ring_enum_ltc,
 	.get_gpc_count = gm20b_priv_ring_get_gpc_count,
 	.get_fbp_count = gm20b_priv_ring_get_fbp_count,

drivers/gpu/nvgpu/hal/init/hal_gm20b.c

@@ -1032,7 +1032,6 @@ static const struct gops_falcon gm20b_ops_falcon = {
 static const struct gops_priv_ring gm20b_ops_priv_ring = {
 	.enable_priv_ring = gm20b_priv_ring_enable,
 	.isr = gm20b_priv_ring_isr,
-	.set_ppriv_timeout_settings = gm20b_priv_set_timeout_settings,
 	.enum_ltc = gm20b_priv_ring_enum_ltc,
 	.get_gpc_count = gm20b_priv_ring_get_gpc_count,
 	.get_fbp_count = gm20b_priv_ring_get_fbp_count,

drivers/gpu/nvgpu/hal/init/hal_gv11b.c

@@ -1421,7 +1421,6 @@ static const struct gops_priv_ring gv11b_ops_priv_ring = {
 	.isr_handle_0 = gp10b_priv_ring_isr_handle_0,
 	.isr_handle_1 = gp10b_priv_ring_isr_handle_1,
 	.decode_error_code = gp10b_priv_ring_decode_error_code,
-	.set_ppriv_timeout_settings = gm20b_priv_set_timeout_settings,
 	.enum_ltc = gm20b_priv_ring_enum_ltc,
 	.get_gpc_count = gm20b_priv_ring_get_gpc_count,
 	.get_fbp_count = gm20b_priv_ring_get_fbp_count,

drivers/gpu/nvgpu/hal/init/hal_tu104.c

@@ -1516,7 +1516,6 @@ static const struct gops_priv_ring tu104_ops_priv_ring = {
 	.isr_handle_0 = gp10b_priv_ring_isr_handle_0,
 	.isr_handle_1 = gp10b_priv_ring_isr_handle_1,
 	.decode_error_code = gp10b_priv_ring_decode_error_code,
-	.set_ppriv_timeout_settings = NULL,
 	.enum_ltc = gm20b_priv_ring_enum_ltc,
 	.get_gpc_count = gm20b_priv_ring_get_gpc_count,
 	.get_fbp_count = gm20b_priv_ring_get_fbp_count,

drivers/gpu/nvgpu/hal/priv_ring/priv_ring_gm20b.h

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2011-2021, NVIDIA CORPORATION.  All rights reserved.
+ * Copyright (c) 2011-2022, NVIDIA CORPORATION.  All rights reserved.
  *
  * Permission is hereby granted, free of charge, to any person obtaining a
  * copy of this software and associated documentation files (the "Software"),
@@ -54,7 +54,6 @@ struct gk20a;
 void gm20b_priv_ring_isr(struct gk20a *g);
 #endif
 int gm20b_priv_ring_enable(struct gk20a *g);
-void gm20b_priv_set_timeout_settings(struct gk20a *g);
 u32 gm20b_priv_ring_enum_ltc(struct gk20a *g);
 
 u32 gm20b_priv_ring_get_gpc_count(struct gk20a *g);

drivers/gpu/nvgpu/hal/priv_ring/priv_ring_gm20b_fusa.c

@@ -1,7 +1,7 @@
 /*
  * GM20B priv ring
  *
- * Copyright (c) 2011-2021, NVIDIA CORPORATION.  All rights reserved.
+ * Copyright (c) 2011-2022, NVIDIA CORPORATION.  All rights reserved.
  *
  * Permission is hereby granted, free of charge, to any person obtaining a
  * copy of this software and associated documentation files (the "Software"),
@@ -95,16 +95,6 @@ int gm20b_priv_ring_enable(struct gk20a *g)
 	return 0;
 }
 
-void gm20b_priv_set_timeout_settings(struct gk20a *g)
-{
-	/*
-	 * Bug 1340570: increase the clock timeout to avoid potential
-	 * operation failure at high gpcclk rate. Default values are 0x400.
-	 */
-	nvgpu_writel(g, pri_ringstation_sys_master_config_r(0x15), 0x800);
-	nvgpu_writel(g, pri_ringstation_gpc_master_config_r(0xa), 0x800);
-}
-
 u32 gm20b_priv_ring_enum_ltc(struct gk20a *g)
 {
 	return nvgpu_readl(g, pri_ringmaster_enum_ltc_r());

drivers/gpu/nvgpu/hal/priv_ring/priv_ring_gp10b.h

@@ -1,7 +1,7 @@
 /*
  * GP10B PRIV ringmaster
  *
- * Copyright (c) 2011-2020, NVIDIA CORPORATION.  All rights reserved.
+ * Copyright (c) 2011-2022, NVIDIA CORPORATION.  All rights reserved.
  *
  * Permission is hereby granted, free of charge, to any person obtaining a
  * copy of this software and associated documentation files (the "Software"),
@@ -26,9 +26,6 @@
 
 struct gk20a;
 
-#define GP10B_PRIV_RING_POLL_CLEAR_INTR_RETRIES	100
-#define GP10B_PRIV_RING_POLL_CLEAR_INTR_UDELAY	20
-
 void gp10b_priv_ring_isr(struct gk20a *g);
 void gp10b_priv_ring_decode_error_code(struct gk20a *g, u32 error_code);
 void gp10b_priv_ring_isr_handle_0(struct gk20a *g, u32 status0);

drivers/gpu/nvgpu/hal/priv_ring/priv_ring_gp10b_fusa.c

@@ -37,6 +37,9 @@
 
 #include "priv_ring_gp10b.h"
 
+static const u32 poll_retries = 100;
+static const u32 poll_delay = 20;
+
 static const char *const error_type_badf1xyy[] = {
 	"client timeout",
 	"decode error",
@@ -204,9 +207,9 @@ void gp10b_priv_ring_isr_handle_1(struct gk20a *g, u32 status1)
 
 void gp10b_priv_ring_isr(struct gk20a *g)
 {
+	u32 retries = poll_retries;
 	u32 status0, status1;
 	u32 cmd;
-	s32 retry;
 
 	status0 = nvgpu_readl(g, pri_ringmaster_intr_status0_r());
 	status1 = nvgpu_readl(g, pri_ringmaster_intr_status1_r());
@@ -224,18 +227,17 @@ void gp10b_priv_ring_isr(struct gk20a *g)
 	nvgpu_writel(g, pri_ringmaster_command_r(), cmd);
 
 	/* poll for clear interrupt done */
-	retry = GP10B_PRIV_RING_POLL_CLEAR_INTR_RETRIES;
 
 	cmd = pri_ringmaster_command_cmd_v(
 		nvgpu_readl(g, pri_ringmaster_command_r()));
-	while ((cmd != pri_ringmaster_command_cmd_no_cmd_v()) && (retry != 0)) {
+	while ((cmd != pri_ringmaster_command_cmd_no_cmd_v()) && (retries != 0U)) {
-		nvgpu_udelay(GP10B_PRIV_RING_POLL_CLEAR_INTR_UDELAY);
+		nvgpu_udelay(poll_delay);
 		cmd = pri_ringmaster_command_cmd_v(
 			nvgpu_readl(g, pri_ringmaster_command_r()));
-		retry--;
+		retries--;
 	}
 
-	if (retry == 0) {
+	if (retries == 0U) {
 		nvgpu_err(g, "priv ringmaster intr ack failed");
 	}
 }

drivers/gpu/nvgpu/hal/vgpu/init/vgpu_hal_ga10b.c

@@ -1026,7 +1026,6 @@ static const struct gops_falcon vgpu_ga10b_ops_falcon = {
 static const struct gops_priv_ring vgpu_ga10b_ops_priv_ring = {
 	.enable_priv_ring = NULL,
 	.isr = NULL,
-	.set_ppriv_timeout_settings = NULL,
 	.enum_ltc = NULL,
 	.get_gpc_count = vgpu_gr_get_gpc_count,
 };

drivers/gpu/nvgpu/hal/vgpu/init/vgpu_hal_gv11b.c

@@ -996,7 +996,6 @@ static const struct gops_falcon vgpu_gv11b_ops_falcon = {
 static const struct gops_priv_ring vgpu_gv11b_ops_priv_ring = {
 	.enable_priv_ring = NULL,
 	.isr = NULL,
-	.set_ppriv_timeout_settings = NULL,
 	.enum_ltc = NULL,
 	.get_gpc_count = vgpu_gr_get_gpc_count,
 };

drivers/gpu/nvgpu/include/nvgpu/gops/priv_ring.h

@@ -167,25 +167,6 @@ struct gops_priv_ring {
 
 	void (*isr_handle_1)(struct gk20a *g, u32 status1);
 
-	/**
-	 * @brief Sets Priv ring timeout value in cycles.
-	 * @brief Sets Priv ring timeout value in cycles when initializing GR H/W unit.
-	 *
-	 * @param g [in]		Pointer to GPU driver struct.
-	 * - The function does not perform validation of g parameter.
-	 *
-	 * This functions sets h/w specified timeout value in the number of
-	 * cycles after sending a priv request. If timeout is exceeded then
-	 * timeout error is reported back via \ref #isr_stall "g->ops.mc.isr_stall(g)".
-	 *
-	 * Steps:
-	 *       - Write \a 0x800 to register pri_ringstation_sys_master_config_r()
-	 *         at offset 0x15.
-	 *       - Write \a 0x800 to register pri_ringstation_gpc_master_config_r()
-	 *         at offset 0xa.
-	 */
-
-	void (*set_ppriv_timeout_settings)(struct gk20a *g);
 	/**
 	 * @brief Returns number of enumerated Level Two Cache (LTC) chiplets.
 	 *

libs/dgpu/libnvgpu-drv-dgpu_safe.export

@@ -73,7 +73,6 @@ gm20b_top_get_max_lts_per_ltc
 gm20b_top_get_num_ltcs
 gm20b_fuse_status_opt_fbp
 gm20b_priv_ring_enable
-gm20b_priv_set_timeout_settings
 gm20b_priv_ring_enum_ltc
 gm20b_priv_ring_get_gpc_count
 gm20b_priv_ring_get_fbp_count

libs/igpu/libnvgpu-drv-igpu_safe.export

@@ -73,7 +73,6 @@ gm20b_top_get_max_lts_per_ltc
 gm20b_top_get_num_ltcs
 gm20b_fuse_status_opt_fbp
 gm20b_priv_ring_enable
-gm20b_priv_set_timeout_settings
 gm20b_priv_ring_enum_ltc
 gm20b_priv_ring_get_gpc_count
 gm20b_priv_ring_get_fbp_count

userspace/required_tests.ini

@@ -996,7 +996,6 @@ test_get_gpc_count.priv_ring_get_gpc_count=0
 test_priv_ring_free_reg_space.priv_ring_free_reg_space=0
 test_priv_ring_isr.priv_ring_isr=0
 test_priv_ring_setup.priv_ring_setup=0
-test_set_ppriv_timeout_settings.priv_ring_set_ppriv_timeout_settings=0
 
 [ptimer]
 ptimer_test_free_env.ptimer_free_env=0

userspace/units/gr/init/nvgpu-gr-init.c

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2019-2020, NVIDIA CORPORATION.  All rights reserved.
+ * Copyright (c) 2019-2022, NVIDIA CORPORATION.  All rights reserved.
  *
  * Permission is hereby granted, free of charge, to any person obtaining a
  * copy of this software and associated documentation files (the "Software"),
@@ -355,7 +355,6 @@ static int test_gr_init_setup_hw_error(struct gk20a *g)
 {
 	int err;
 
-	g->ops.priv_ring.set_ppriv_timeout_settings = NULL;
 	g->ops.gr.init.ecc_scrub_reg = NULL;
 	err = nvgpu_gr_init_support(g);
 	if (err != 0) {
@@ -369,8 +368,6 @@ static int test_gr_init_setup_hw_error(struct gk20a *g)
 	if (err == 0) {
 		return UNIT_FAIL;
 	}
-	g->ops.priv_ring.set_ppriv_timeout_settings =
-		gr_init_gops.priv_ring.set_ppriv_timeout_settings;
 	g->ops.gr.init.ecc_scrub_reg =
 		gr_init_gops.gr.init.ecc_scrub_reg;
 

userspace/units/priv_ring/nvgpu-priv_ring.c

@@ -118,8 +118,6 @@ int test_priv_ring_setup(struct unit_module *m, struct gk20a *g, void *args)
 	g->ops.priv_ring.isr_handle_0 = gp10b_priv_ring_isr_handle_0;
 	g->ops.priv_ring.isr_handle_1 = gp10b_priv_ring_isr_handle_1;
 	g->ops.priv_ring.decode_error_code = gp10b_priv_ring_decode_error_code;
-	g->ops.priv_ring.set_ppriv_timeout_settings =
-					gm20b_priv_set_timeout_settings;
 	g->ops.priv_ring.enum_ltc = gm20b_priv_ring_enum_ltc;
 	g->ops.priv_ring.get_gpc_count = gm20b_priv_ring_get_gpc_count;
 	g->ops.priv_ring.get_fbp_count = gm20b_priv_ring_get_fbp_count;
@@ -255,31 +253,6 @@ end:
 	return ret;
 }
 
-int test_set_ppriv_timeout_settings(struct unit_module *m, struct gk20a *g,
-								void *args)
-{
-	int ret = UNIT_SUCCESS;
-	u32 val_sys;
-	u32 val_gpc;
-
-	/* Call set_ppriv_timeout_settings HAL to set the timeout values
-	 * to 0x800.
-	 */
-	g->ops.priv_ring.set_ppriv_timeout_settings(g);
-
-	/* Read back the registers to make sure the timeouts are set to 0x800 */
-	val_sys = nvgpu_posix_io_readl_reg_space(g,
-				pri_ringstation_sys_master_config_r(0x15));
-	val_gpc = nvgpu_posix_io_readl_reg_space(g,
-				pri_ringstation_gpc_master_config_r(0xa));
-	if ((val_sys != 0x800) || (val_gpc != 0x800)) {
-		unit_err(m, "Timeout setting failed.\n");
-		ret = UNIT_FAIL;
-	}
-
-	return ret;
-}
-
 int test_enum_ltc(struct unit_module *m, struct gk20a *g, void *args)
 {
 	int ret = UNIT_SUCCESS;
@@ -413,8 +386,6 @@ int test_decode_error_code(struct unit_module *m, struct gk20a *g, void *args)
 struct unit_module_test priv_ring_tests[] = {
 	UNIT_TEST(priv_ring_setup,	       test_priv_ring_setup,   NULL, 0),
 	UNIT_TEST(priv_ring_enable_priv_ring,  test_enable_priv_ring,  NULL, 0),
-	UNIT_TEST(priv_ring_set_ppriv_timeout_settings,
-				    test_set_ppriv_timeout_settings,   NULL, 0),
 	UNIT_TEST(priv_ring_enum_ltc,          test_enum_ltc,          NULL, 0),
 	UNIT_TEST(priv_ring_get_gpc_count,     test_get_gpc_count,     NULL, 0),
 	UNIT_TEST(priv_ring_get_fbp_count,     test_get_fbp_count,     NULL, 0),

userspace/units/priv_ring/nvgpu-priv_ring.h

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2019-2021, NVIDIA CORPORATION.  All rights reserved.
+ * Copyright (c) 2019-2022, NVIDIA CORPORATION.  All rights reserved.
  *
  * Permission is hereby granted, free of charge, to any person obtaining a
  * copy of this software and associated documentation files (the "Software"),
@@ -93,29 +93,6 @@ int test_priv_ring_free_reg_space(struct unit_module *m, struct gk20a *g, void *
  */
 int test_enable_priv_ring(struct unit_module *m, struct gk20a *g, void *args);
 
-/**
- * Test specification for: test_set_ppriv_timeout_settings
- *
- * Description: Verify the priv_ring.set_ppriv_timeout_settings HAL.
- *
- * Test Type: Feature
- *
- * Targets: gops_priv_ring.set_ppriv_timeout_settings,
- *          gm20b_priv_set_timeout_settings
- *
- * Input: test_priv_ring_setup() has been executed.
- *
- * Steps:
- * - Call set_ppriv_timeout_settings HAL to set the timeout values to 0x800.
- * - Read back the registers to make sure the timeouts are set to 0x800.
- *
- * Output:
- * - UNIT_FAIL if above HAL fails to set timeouts.
- * - UNIT_SUCCESS otherwise.
- */
-int test_set_ppriv_timeout_settings(struct unit_module *m, struct gk20a *g,
-								void *args);
-
 /**
  * Test specification for: test_enum_ltc
  *