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gpu: nvgpu: gv10x volt rail boardobj changes
- Created volt ops under pmu_ver to support volt_set_voltage, volt_get_voltage & volt_send_load_cmd_to_pmu. - Renamed volt load, set_voltage & get_voltage gp10x method names. - Added new volt load, set_voltage & get_voltage methods for gv10x using RPC & added code to handle ack in pmu_rpc_handler() along with struct rail_list changes. - Updated volt ops of gp106 & gv100 to point to respective methods. - Added member volt_dev_idx_ipc_vmin & volt_scale_exp_pwr_equ_idx to "struct nv_pmu_volt_volt_rail_boardobj_set" & "struct voltage_rail" made changes to update members as needed. - Added member volt_scale_exp_pwr_equ_idx to "struct vbios_voltage_rail_table_1x_entry" to read value from VBIOS table & update rail boardobj set interface. - Defines for volt RPC "NV_PMU_RPC_ID_VOLT_*" - Define struct's volt load, set_voltage & get_voltage to execute volt RPC. Change-Id: I4a41adcf7536468beaa8a73f551b1d608aabd161 Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1659728 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
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@@ -1,5 +1,5 @@
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/*
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* Copyright (c) 2016-2017, NVIDIA CORPORATION. All rights reserved.
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* Copyright (c) 2016-2018, NVIDIA CORPORATION. All rights reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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@@ -34,8 +34,10 @@ u8 volt_rail_volt_domain_convert_to_idx(struct gk20a *g, u8 volt_domain)
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{
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switch (g->perf_pmu.volt.volt_rail_metadata.volt_domain_hal) {
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case CTRL_VOLT_DOMAIN_HAL_GP10X_SINGLE_RAIL:
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if (volt_domain == CTRL_BOARDOBJ_IDX_INVALID)
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switch (volt_domain) {
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case CTRL_VOLT_DOMAIN_LOGIC:
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return 0;
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}
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break;
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case CTRL_VOLT_DOMAIN_HAL_GP10X_SPLIT_RAIL:
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switch (volt_domain) {
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@@ -63,6 +65,22 @@ u32 volt_rail_volt_dev_register(struct gk20a *g, struct voltage_rail
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status = -EINVAL;
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goto exit;
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}
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} else if (operation_type ==
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CTRL_VOLT_VOLT_DEVICE_OPERATION_TYPE_IPC_VMIN) {
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if (pvolt_rail->volt_dev_idx_ipc_vmin ==
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CTRL_BOARDOBJ_IDX_INVALID) {
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pvolt_rail->volt_dev_idx_ipc_vmin = volt_dev_idx;
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/*
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* Exit on purpose as we do not want to register
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* IPC_VMIN device against the rail to avoid
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* setting current voltage instead of
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* IPC Vmin voltage.
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*/
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goto exit;
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} else {
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status = -EINVAL;
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goto exit;
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}
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} else {
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goto exit;
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}
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@@ -136,6 +154,9 @@ static u32 volt_rail_init_pmudata_super(struct gk20a *g,
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prail->volt_margin_limit_vfe_equ_idx;
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rail_pmu_data->pwr_equ_idx = prail->pwr_equ_idx;
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rail_pmu_data->volt_dev_idx_default = prail->volt_dev_idx_default;
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rail_pmu_data->volt_scale_exp_pwr_equ_idx =
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prail->volt_scale_exp_pwr_equ_idx;
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rail_pmu_data->volt_dev_idx_ipc_vmin = prail->volt_dev_idx_ipc_vmin;
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for (i = 0; i < CTRL_VOLT_RAIL_VOLT_DELTA_MAX_ENTRIES; i++) {
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rail_pmu_data->volt_delta_uv[i] = prail->volt_delta_uv[i] +
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@@ -187,6 +208,8 @@ static struct voltage_rail *construct_volt_rail(struct gk20a *g, void *pargs)
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ptemp_rail->vmin_limit_vfe_equ_idx;
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board_obj_volt_rail_ptr->volt_margin_limit_vfe_equ_idx =
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ptemp_rail->volt_margin_limit_vfe_equ_idx;
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board_obj_volt_rail_ptr->volt_scale_exp_pwr_equ_idx =
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ptemp_rail->volt_scale_exp_pwr_equ_idx;
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gk20a_dbg_info("Done");
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@@ -284,6 +307,14 @@ static u32 volt_get_volt_rail_table(struct gk20a *g,
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rail_type_data.volt_rail.ov_limit_vfe_equ_idx =
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(u8)entry.ov_limit_vfe_equ_idx;
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if (header.table_entry_size >=
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NV_VBIOS_VOLTAGE_RAIL_1X_ENTRY_SIZE_0C)
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rail_type_data.volt_rail.volt_scale_exp_pwr_equ_idx =
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(u8)entry.volt_scale_exp_pwr_equ_idx;
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else
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rail_type_data.volt_rail.volt_scale_exp_pwr_equ_idx =
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CTRL_BOARDOBJ_IDX_INVALID;
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if (header.table_entry_size >=
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NV_VBIOS_VOLTAGE_RAIL_1X_ENTRY_SIZE_0B)
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rail_type_data.volt_rail.volt_margin_limit_vfe_equ_idx =
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