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gpu: nvgpu: gp10b: fix MISRA Rule 10.4 Violations
MISRA Rule 10.4 only allows the usage of arithmetic operations on operands of the same essential type category. Adding "U" at the end of the integer literals to have same type of operands when an arithmetic operation is performed. This fixes violations where an arithmetic operation is performed on signed and unsigned int types. JIRA NVGPU-992 Change-Id: I6bcb60d08941bc71adbfd3e832e9a6022a3955f7 Signed-off-by: Sai Nikhil <snikhil@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1829577 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
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Sai Nikhil
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@@ -46,7 +46,7 @@
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#include <nvgpu/hw/gp10b/hw_fifo_gp10b.h>
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#include <nvgpu/hw/gp10b/hw_ctxsw_prog_gp10b.h>
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#define GFXP_WFI_TIMEOUT_COUNT_DEFAULT 100000
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#define GFXP_WFI_TIMEOUT_COUNT_DEFAULT 100000U
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bool gr_gp10b_is_valid_class(struct gk20a *g, u32 class_num)
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{
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@@ -541,10 +541,10 @@ int gr_gp10b_add_zbc_color(struct gk20a *g, struct gr_gk20a *gr,
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color_val->color_ds[2]);
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nvgpu_writel_loop(g, gr_gpcs_swdx_dss_zbc_color_a_r(index),
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color_val->color_ds[3]);
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zbc_c = gk20a_readl(g, zbc_c_format_reg + (index & ~3));
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zbc_c &= ~(0x7f << ((index % 4) * 7));
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zbc_c |= color_val->format << ((index % 4) * 7);
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nvgpu_writel_loop(g, zbc_c_format_reg + (index & ~3), zbc_c);
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zbc_c = gk20a_readl(g, zbc_c_format_reg + (index & ~3U));
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zbc_c &= ~(0x7fU << ((index % 4U) * 7U));
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zbc_c |= color_val->format << ((index % 4U) * 7U);
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nvgpu_writel_loop(g, zbc_c_format_reg + (index & ~3U), zbc_c);
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return 0;
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}
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@@ -570,10 +570,10 @@ int gr_gp10b_add_zbc_depth(struct gk20a *g, struct gr_gk20a *gr,
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gr->zbc_dep_tbl[index].ref_cnt++;
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gk20a_writel(g, gr_gpcs_swdx_dss_zbc_z_r(index), depth_val->depth);
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zbc_z = gk20a_readl(g, zbc_z_format_reg + (index & ~3));
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zbc_z = gk20a_readl(g, zbc_z_format_reg + (index & ~3U));
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zbc_z &= ~(U32(0x7f) << (index % 4U) * 7U);
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zbc_z |= depth_val->format << (index % 4) * 7;
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gk20a_writel(g, zbc_z_format_reg + (index & ~3), zbc_z);
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zbc_z |= depth_val->format << (index % 4U) * 7U;
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gk20a_writel(g, zbc_z_format_reg + (index & ~3U), zbc_z);
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return 0;
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}
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@@ -755,7 +755,7 @@ void gr_gp10b_set_alpha_circular_buffer_size(struct gk20a *g, u32 data)
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struct gr_gk20a *gr = &g->gr;
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u32 gpc_index, ppc_index, stride, val;
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u32 pd_ab_max_output;
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u32 alpha_cb_size = data * 4;
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u32 alpha_cb_size = data * 4U;
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u32 gpc_stride = nvgpu_get_litter_value(g, GPU_LIT_GPC_STRIDE);
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u32 ppc_in_gpc_stride = nvgpu_get_litter_value(g, GPU_LIT_PPC_IN_GPC_STRIDE);
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@@ -809,7 +809,7 @@ void gr_gp10b_set_circular_buffer_size(struct gk20a *g, u32 data)
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{
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struct gr_gk20a *gr = &g->gr;
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u32 gpc_index, ppc_index, stride, val;
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u32 cb_size_steady = data * 4, cb_size;
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u32 cb_size_steady = data * 4U, cb_size;
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u32 gpc_stride = nvgpu_get_litter_value(g, GPU_LIT_GPC_STRIDE);
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u32 ppc_in_gpc_stride = nvgpu_get_litter_value(g, GPU_LIT_PPC_IN_GPC_STRIDE);
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@@ -1227,7 +1227,7 @@ void gr_gp10b_update_ctxsw_preemption_mode(struct gk20a *g,
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addr = (u64_lo32(gr_ctx->betacb_ctxsw_buffer.gpu_va) >>
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gr_gpcs_setup_attrib_cb_base_addr_39_12_align_bits_v()) |
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(u64_hi32(gr_ctx->betacb_ctxsw_buffer.gpu_va) <<
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(32 - gr_gpcs_setup_attrib_cb_base_addr_39_12_align_bits_v()));
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(32U - gr_gpcs_setup_attrib_cb_base_addr_39_12_align_bits_v()));
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nvgpu_log_info(g, "attrib cb addr : 0x%016x", addr);
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g->ops.gr.commit_global_attrib_cb(g, gr_ctx, addr, true);
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@@ -1235,7 +1235,7 @@ void gr_gp10b_update_ctxsw_preemption_mode(struct gk20a *g,
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addr = (u64_lo32(gr_ctx->pagepool_ctxsw_buffer.gpu_va) >>
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gr_scc_pagepool_base_addr_39_8_align_bits_v()) |
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(u64_hi32(gr_ctx->pagepool_ctxsw_buffer.gpu_va) <<
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(32 - gr_scc_pagepool_base_addr_39_8_align_bits_v()));
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(32U - gr_scc_pagepool_base_addr_39_8_align_bits_v()));
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size = gr_ctx->pagepool_ctxsw_buffer.size;
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if (size == g->ops.gr.pagepool_default_size(g)) {
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@@ -1247,7 +1247,7 @@ void gr_gp10b_update_ctxsw_preemption_mode(struct gk20a *g,
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addr = (u64_lo32(gr_ctx->spill_ctxsw_buffer.gpu_va) >>
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gr_gpc0_swdx_rm_spill_buffer_addr_39_8_align_bits_v()) |
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(u64_hi32(gr_ctx->spill_ctxsw_buffer.gpu_va) <<
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(32 - gr_gpc0_swdx_rm_spill_buffer_addr_39_8_align_bits_v()));
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(32U - gr_gpc0_swdx_rm_spill_buffer_addr_39_8_align_bits_v()));
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size = gr_ctx->spill_ctxsw_buffer.size /
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gr_gpc0_swdx_rm_spill_buffer_size_256b_byte_granularity_v();
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@@ -1417,7 +1417,7 @@ int gr_gp10b_dump_gr_status_regs(struct gk20a *g,
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static bool gr_activity_empty_or_preempted(u32 val)
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{
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while(val != 0U) {
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u32 v = val & 7;
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u32 v = val & 7U;
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if (v != gr_activity_4_gpc0_empty_v() &&
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v != gr_activity_4_gpc0_preempted_v()) {
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return false;
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@@ -1447,7 +1447,7 @@ int gr_gp10b_wait_empty(struct gk20a *g, unsigned long duration_ms,
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only when gr_status is read */
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gr_status = gk20a_readl(g, gr_status_r());
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ctxsw_active = gr_status & 1<<7;
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ctxsw_active = gr_status & BIT32(7);
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activity0 = gk20a_readl(g, gr_activity_0_r());
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activity1 = gk20a_readl(g, gr_activity_1_r());
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@@ -1456,7 +1456,7 @@ int gr_gp10b_wait_empty(struct gk20a *g, unsigned long duration_ms,
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gr_busy = !(gr_activity_empty_or_preempted(activity0) &&
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gr_activity_empty_or_preempted(activity1) &&
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activity2 == 0 &&
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activity2 == 0U &&
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gr_activity_empty_or_preempted(activity4));
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if (!gr_busy && !ctxsw_active) {
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@@ -1464,7 +1464,7 @@ int gr_gp10b_wait_empty(struct gk20a *g, unsigned long duration_ms,
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return 0;
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}
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nvgpu_usleep_range(delay, delay * 2);
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nvgpu_usleep_range(delay, delay * 2U);
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delay = min_t(u32, delay << 1, GR_IDLE_CHECK_MAX);
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} while (nvgpu_timeout_expired(&timeout) == 0);
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@@ -1551,13 +1551,13 @@ int gr_gp10b_load_smid_config(struct gk20a *g)
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}
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/* Each NV_PGRAPH_PRI_CWD_GPC_TPC_ID can store 4 TPCs.*/
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for (i = 0; i <= ((g->gr.tpc_count-1) / 4); i++) {
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for (i = 0U; i <= ((g->gr.tpc_count-1U) / 4U); i++) {
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u32 reg = 0;
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u32 bit_stride = gr_cwd_gpc_tpc_id_gpc0_s() +
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gr_cwd_gpc_tpc_id_tpc0_s();
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for (j = 0; j < 4; j++) {
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u32 sm_id = (i * 4) + j;
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for (j = 0U; j < 4U; j++) {
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u32 sm_id = (i * 4U) + j;
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u32 bits;
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if (sm_id >= g->gr.tpc_count) {
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@@ -1571,8 +1571,8 @@ int gr_gp10b_load_smid_config(struct gk20a *g)
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gr_cwd_gpc_tpc_id_tpc0_f(tpc_index);
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reg |= bits << (j * bit_stride);
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tpc_sm_id[gpc_index + max_gpcs * ((tpc_index & 4) >> 2)]
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|= sm_id << (bit_stride * (tpc_index & 3));
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tpc_sm_id[gpc_index + max_gpcs * ((tpc_index & 4U) >> 2U)]
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|= sm_id << (bit_stride * (tpc_index & 3U));
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}
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gk20a_writel(g, gr_cwd_gpc_tpc_id_r(i), reg);
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}
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@@ -1602,7 +1602,7 @@ int gr_gp10b_init_fs_state(struct gk20a *g)
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gr_gpcs_tpcs_sm_disp_ctrl_re_suppress_disable_f());
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gk20a_writel(g, gr_gpcs_tpcs_sm_disp_ctrl_r(), data);
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if (g->gr.fecs_feature_override_ecc_val != 0) {
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if (g->gr.fecs_feature_override_ecc_val != 0U) {
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gk20a_writel(g,
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gr_fecs_feature_override_ecc_r(),
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g->gr.fecs_feature_override_ecc_val);
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@@ -1616,9 +1616,9 @@ void gr_gp10b_set_gpc_tpc_mask(struct gk20a *g, u32 gpc_index)
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nvgpu_tegra_fuse_write_bypass(g, 0x1);
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nvgpu_tegra_fuse_write_access_sw(g, 0x0);
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if (g->gr.gpc_tpc_mask[gpc_index] == 0x1) {
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if (g->gr.gpc_tpc_mask[gpc_index] == 0x1U) {
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nvgpu_tegra_fuse_write_opt_gpu_tpc0_disable(g, 0x2);
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} else if (g->gr.gpc_tpc_mask[gpc_index] == 0x2) {
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} else if (g->gr.gpc_tpc_mask[gpc_index] == 0x2U) {
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nvgpu_tegra_fuse_write_opt_gpu_tpc0_disable(g, 0x1);
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} else {
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nvgpu_tegra_fuse_write_opt_gpu_tpc0_disable(g, 0x0);
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@@ -1863,7 +1863,7 @@ int gr_gp10b_pre_process_sm_exception(struct gk20a *g,
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gr_gpcs_tpcs_sm_hww_global_esr_timeout_error_pending_f() |
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gr_gpcs_tpcs_sm_hww_global_esr_bpt_pause_pending_f();
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if (warp_esr != 0 || (global_esr & global_mask) != 0) {
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if (warp_esr != 0U || (global_esr & global_mask) != 0U) {
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*ignore_debugger = true;
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nvgpu_log(g, gpu_dbg_fn | gpu_dbg_gpu_dbg,
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@@ -2158,7 +2158,7 @@ int gr_gp10b_suspend_contexts(struct gk20a *g,
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break;
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}
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nvgpu_usleep_range(delay, delay * 2);
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nvgpu_usleep_range(delay, delay * 2U);
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delay = min_t(u32, delay << 1, GR_IDLE_CHECK_MAX);
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} while (nvgpu_timeout_expired(&timeout) == 0);
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@@ -2399,5 +2399,5 @@ void gr_gp10b_init_gfxp_wfi_timeout_count(struct gk20a *g)
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unsigned long gr_gp10b_get_max_gfxp_wfi_timeout_count(struct gk20a *g)
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{
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/* 100msec @ 1GHZ */
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return (100 * 1000 * 1000UL);
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return (100UL * 1000UL * 1000UL);
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}
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@@ -42,16 +42,16 @@ enum {
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PASCAL_DMA_COPY_B = 0xC1B5,
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};
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#define NVC097_SET_GO_IDLE_TIMEOUT 0x022c
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#define NVC097_SET_ALPHA_CIRCULAR_BUFFER_SIZE 0x02dc
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#define NVC097_SET_COALESCE_BUFFER_SIZE 0x1028
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#define NVC097_SET_RD_COALESCE 0x102c
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#define NVC097_SET_CIRCULAR_BUFFER_SIZE 0x1280
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#define NVC097_SET_SHADER_EXCEPTIONS 0x1528
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#define NVC097_SET_BES_CROP_DEBUG3 0x10c4
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#define NVC097_SET_BES_CROP_DEBUG4 0x10b0
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#define NVC0C0_SET_SHADER_EXCEPTIONS 0x1528
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#define NVC0C0_SET_RD_COALESCE 0x0228
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#define NVC097_SET_GO_IDLE_TIMEOUT 0x022cU
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#define NVC097_SET_ALPHA_CIRCULAR_BUFFER_SIZE 0x02dcU
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#define NVC097_SET_COALESCE_BUFFER_SIZE 0x1028U
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#define NVC097_SET_RD_COALESCE 0x102cU
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#define NVC097_SET_CIRCULAR_BUFFER_SIZE 0x1280U
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#define NVC097_SET_SHADER_EXCEPTIONS 0x1528U
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#define NVC097_SET_BES_CROP_DEBUG3 0x10c4U
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#define NVC097_SET_BES_CROP_DEBUG4 0x10b0U
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#define NVC0C0_SET_SHADER_EXCEPTIONS 0x1528U
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#define NVC0C0_SET_RD_COALESCE 0x0228U
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#define NVC097_BES_CROP_DEBUG4_CLAMP_FP_BLEND_TO_INF 0x0U
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#define NVC097_BES_CROP_DEBUG4_CLAMP_FP_BLEND_TO_MAXVAL 0x1U
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@@ -203,7 +203,7 @@ static void __update_pte(struct vm_gk20a *vm,
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pte_w[0] |= gmmu_new_pte_privilege_true_f();
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}
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pte_w[1] = phys_addr >> (24 + gmmu_new_pte_address_shift_v()) |
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pte_w[1] = phys_addr >> (24U + gmmu_new_pte_address_shift_v()) |
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gmmu_new_pte_kind_f(attrs->kind_v) |
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gmmu_new_pte_comptagline_f((u32)(attrs->ctag /
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ctag_granularity));
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@@ -275,7 +275,7 @@ static void update_gmmu_pte_locked(struct vm_gk20a *vm,
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pd_write(g, pd, (size_t)pd_offset + (size_t)1, pte_w[1]);
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}
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#define GP10B_PDE0_ENTRY_SIZE 16
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#define GP10B_PDE0_ENTRY_SIZE 16U
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/*
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* Calculate the pgsz of the pde level
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