From d5b14a389e6c9e57480db51f086920544f954bcd Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Konsta=20H=C3=B6ltt=C3=A4?= Date: Mon, 18 May 2020 08:46:36 +0300 Subject: [PATCH] gpu: nvgpu: do not writel_check zbc broadcast regs MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Use nvgpu_writel() instead of nvgpu_writel_check() for writing the zbc color, depth and stencil values in L2 ZBC registers. Checking that the read value equals is not sensible for broadcast registers, and in these cases it's not necessary to read back the regs to synchronize memory. Bug 2976632 Change-Id: Id40e7d0f435bae5a395b5553c186fc50302f7dea Signed-off-by: Konsta Hölttä Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2345877 Reviewed-by: automaticguardword Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Deepak Nibade Reviewed-by: mobile promotions GVS: Gerrit_Virtual_Submit Tested-by: mobile promotions --- drivers/gpu/nvgpu/hal/ltc/ltc_gm20b.c | 12 +++++------- drivers/gpu/nvgpu/hal/ltc/ltc_gv11b.c | 7 +++---- 2 files changed, 8 insertions(+), 11 deletions(-) diff --git a/drivers/gpu/nvgpu/hal/ltc/ltc_gm20b.c b/drivers/gpu/nvgpu/hal/ltc/ltc_gm20b.c index 670e980df..48b28f0de 100644 --- a/drivers/gpu/nvgpu/hal/ltc/ltc_gm20b.c +++ b/drivers/gpu/nvgpu/hal/ltc/ltc_gm20b.c @@ -122,14 +122,13 @@ void gm20b_ltc_set_zbc_color_entry(struct gk20a *g, { u32 i; - nvgpu_writel_check(g, ltc_ltcs_ltss_dstg_zbc_index_r(), + nvgpu_writel(g, ltc_ltcs_ltss_dstg_zbc_index_r(), ltc_ltcs_ltss_dstg_zbc_index_address_f( nvgpu_safe_add_u32(index, NVGPU_GR_ZBC_STARTOF_TABLE))); for (i = 0; i < ltc_ltcs_ltss_dstg_zbc_color_clear_value__size_1_v(); i++) { - nvgpu_writel_check(g, - ltc_ltcs_ltss_dstg_zbc_color_clear_value_r(i), + nvgpu_writel(g, ltc_ltcs_ltss_dstg_zbc_color_clear_value_r(i), color_l2[i]); } } @@ -141,13 +140,12 @@ void gm20b_ltc_set_zbc_depth_entry(struct gk20a *g, u32 depth_val, u32 index) { - nvgpu_writel_check(g, ltc_ltcs_ltss_dstg_zbc_index_r(), + nvgpu_writel(g, ltc_ltcs_ltss_dstg_zbc_index_r(), ltc_ltcs_ltss_dstg_zbc_index_address_f( nvgpu_safe_add_u32(index, NVGPU_GR_ZBC_STARTOF_TABLE))); - nvgpu_writel_check(g, - ltc_ltcs_ltss_dstg_zbc_depth_clear_value_r(), - depth_val); + nvgpu_writel(g, ltc_ltcs_ltss_dstg_zbc_depth_clear_value_r(), + depth_val); } u32 gm20b_ltc_zbc_table_size(struct gk20a *g) diff --git a/drivers/gpu/nvgpu/hal/ltc/ltc_gv11b.c b/drivers/gpu/nvgpu/hal/ltc/ltc_gv11b.c index 9e906a424..57b0a81c6 100644 --- a/drivers/gpu/nvgpu/hal/ltc/ltc_gv11b.c +++ b/drivers/gpu/nvgpu/hal/ltc/ltc_gv11b.c @@ -42,13 +42,12 @@ void gv11b_ltc_set_zbc_stencil_entry(struct gk20a *g, u32 stencil_depth, u32 index) { - nvgpu_writel_check(g, ltc_ltcs_ltss_dstg_zbc_index_r(), + nvgpu_writel(g, ltc_ltcs_ltss_dstg_zbc_index_r(), ltc_ltcs_ltss_dstg_zbc_index_address_f( nvgpu_safe_add_u32(index, NVGPU_GR_ZBC_STARTOF_TABLE))); - nvgpu_writel_check(g, - ltc_ltcs_ltss_dstg_zbc_stencil_clear_value_r(), - stencil_depth); + nvgpu_writel(g, ltc_ltcs_ltss_dstg_zbc_stencil_clear_value_r(), + stencil_depth); } #endif /* CONFIG_NVGPU_GRAPHICS */