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gpu: nvgpu: tu10x: Add CE diversity gpu characteristic flag

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Tu104 has multiple async-LCE (3), GRCE (2) and PCE (4).
So it is possible to use a different LCE/PCE during redundant
execution. This will allow us to claim very high coverage for
permanent fault.

JIRA NVGPU-4370

Change-Id: Ib39013d8d4f377eb20820db100af57c57592c39d
Signed-off-by: Lakshmanan M <lm@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2243984
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
Reviewed-by: svc-mobile-cert <svc-mobile-cert@nvidia.com>
Reviewed-by: Antony Clince Alex <aalex@nvidia.com>
Reviewed-by: Shashank Singh <shashsingh@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Vaibhav Kachore <vkachore@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
This commit is contained in:
Lakshmanan M
2019-11-21 11:00:44 +05:30
committed by Alex Waterman
parent eb4349548d
commit d6a20e31b3
4 changed files with 25 additions and 2 deletions
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5
drivers/gpu/nvgpu/include/nvgpu/enabled.h
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@@ -243,10 +243,13 @@ struct gk20a;
/** FMON feature Enable */
#define NVGPU_FMON_SUPPORT_ENABLE 83U
/** Copy Engine diversity enable bit */
#define NVGPU_SUPPORT_COPY_ENGINE_DIVERSITY 84U
/*
* Must be greater than the largest bit offset in the above list.
*/
#define NVGPU_MAX_ENABLED_BITS 84U
#define NVGPU_MAX_ENABLED_BITS 85U
/**
* @brief Check if the passed flag is enabled.