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gpu: nvgpu: fix MISRA Rule 5.1 violation

Browse Source 
BVEC changes for nvgpu_rc_pbdma_fault and nvgpu_rc_mmu_fault
started reporting below MISRA issue.

kernel/nvgpu/drivers/gpu/nvgpu/common/fifo/tsg.c:321:
  1. misra_c_2012_rule_5_1_violation: Declaration with identifier
     "nvgpu_tsg_unbind_channel_check_hw_state", which is ambiguous.
kernel/nvgpu/drivers/gpu/nvgpu/common/fifo/tsg.c:349:
  2. other_declaration: The first 31 characters of identifiers
     "nvgpu_tsg_unbind_channel_check_ctx_reload" and
     "nvgpu_tsg_unbind_channel_check_hw_state" are identical.

Do below renames to fix the issue. Doing both for consistency.

s/nvgpu_tsg_unbind_channel_check_hw_state/nvgpu_tsg_unbind_channel_hw_state_check
s/nvgpu_tsg_unbind_channel_check_ctx_reload/nvgpu_tsg_unbind_channel_ctx_reload_check

JIRA NVGPU-6772

Change-Id: Ib92cabe11c486621351bf15ddb86e20d16d514c4
Signed-off-by: Sagar Kamble <skamble@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2584152
(cherry picked from commit a619f259c6a4ffccb05550767212989af60c2a90)
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2706551
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-cert <svc-mobile-cert@nvidia.com>
Reviewed-by: Vaibhav Kachore <vkachore@nvidia.com>
GVS: Gerrit_Virtual_Submit
This commit is contained in:
Sagar Kamble
2021-08-27 10:32:16 +05:30
committed by mobile promotions
parent 162d7ec32d
commit d82400d2b8
12 changed files with 26 additions and 26 deletions
Download Patch File Download Diff File Expand all files Collapse all files

4
drivers/gpu/nvgpu/common/fifo/tsg.c
View File

@@ -396,7 +396,7 @@ fail:
} }
int nvgpu_tsg_unbind_channel_check_hw_state(struct nvgpu_tsg *tsg, int nvgpu_tsg_unbind_channel_hw_state_check(struct nvgpu_tsg *tsg,
struct nvgpu_channel *ch) struct nvgpu_channel *ch)
{ {
struct gk20a *g = ch->g; struct gk20a *g = ch->g;
@@ -423,7 +423,7 @@ int nvgpu_tsg_unbind_channel_check_hw_state(struct nvgpu_tsg *tsg,
return err; return err;
} }
void nvgpu_tsg_unbind_channel_check_ctx_reload(struct nvgpu_tsg *tsg, void nvgpu_tsg_unbind_channel_ctx_reload_check(struct nvgpu_tsg *tsg,
struct nvgpu_channel *ch, struct nvgpu_channel *ch,
struct nvgpu_channel_hw_state *hw_state) struct nvgpu_channel_hw_state *hw_state)
{ {

4
drivers/gpu/nvgpu/hal/init/hal_ga100.c
View File

@@ -1200,9 +1200,9 @@ static const struct gops_tsg ga100_ops_tsg = {
.bind_channel = NULL, .bind_channel = NULL,
.bind_channel_eng_method_buffers = gv11b_tsg_bind_channel_eng_method_buffers, .bind_channel_eng_method_buffers = gv11b_tsg_bind_channel_eng_method_buffers,
.unbind_channel = NULL, .unbind_channel = NULL,
.unbind_channel_check_hw_state = nvgpu_tsg_unbind_channel_check_hw_state, .unbind_channel_check_hw_state = nvgpu_tsg_unbind_channel_hw_state_check,
.unbind_channel_check_hw_next = ga10b_tsg_unbind_channel_check_hw_next, .unbind_channel_check_hw_next = ga10b_tsg_unbind_channel_check_hw_next,
.unbind_channel_check_ctx_reload = nvgpu_tsg_unbind_channel_check_ctx_reload, .unbind_channel_check_ctx_reload = nvgpu_tsg_unbind_channel_ctx_reload_check,
.unbind_channel_check_eng_faulted = gv11b_tsg_unbind_channel_check_eng_faulted, .unbind_channel_check_eng_faulted = gv11b_tsg_unbind_channel_check_eng_faulted,
#ifdef CONFIG_NVGPU_KERNEL_MODE_SUBMIT #ifdef CONFIG_NVGPU_KERNEL_MODE_SUBMIT
.check_ctxsw_timeout = nvgpu_tsg_check_ctxsw_timeout, .check_ctxsw_timeout = nvgpu_tsg_check_ctxsw_timeout,

4
drivers/gpu/nvgpu/hal/init/hal_ga10b.c
View File

@@ -1211,9 +1211,9 @@ static const struct gops_tsg ga10b_ops_tsg = {
.bind_channel = NULL, .bind_channel = NULL,
.bind_channel_eng_method_buffers = gv11b_tsg_bind_channel_eng_method_buffers, .bind_channel_eng_method_buffers = gv11b_tsg_bind_channel_eng_method_buffers,
.unbind_channel = NULL, .unbind_channel = NULL,
.unbind_channel_check_hw_state = nvgpu_tsg_unbind_channel_check_hw_state, .unbind_channel_check_hw_state = nvgpu_tsg_unbind_channel_hw_state_check,
.unbind_channel_check_hw_next = ga10b_tsg_unbind_channel_check_hw_next, .unbind_channel_check_hw_next = ga10b_tsg_unbind_channel_check_hw_next,
.unbind_channel_check_ctx_reload = nvgpu_tsg_unbind_channel_check_ctx_reload, .unbind_channel_check_ctx_reload = nvgpu_tsg_unbind_channel_ctx_reload_check,
.unbind_channel_check_eng_faulted = gv11b_tsg_unbind_channel_check_eng_faulted, .unbind_channel_check_eng_faulted = gv11b_tsg_unbind_channel_check_eng_faulted,
#ifdef CONFIG_NVGPU_KERNEL_MODE_SUBMIT #ifdef CONFIG_NVGPU_KERNEL_MODE_SUBMIT
.check_ctxsw_timeout = nvgpu_tsg_check_ctxsw_timeout, .check_ctxsw_timeout = nvgpu_tsg_check_ctxsw_timeout,

4
drivers/gpu/nvgpu/hal/init/hal_gm20b.c
View File

@@ -750,9 +750,9 @@ static const struct gops_tsg gm20b_ops_tsg = {
.disable = nvgpu_tsg_disable, .disable = nvgpu_tsg_disable,
.bind_channel = NULL, .bind_channel = NULL,
.unbind_channel = NULL, .unbind_channel = NULL,
.unbind_channel_check_hw_state = nvgpu_tsg_unbind_channel_check_hw_state, .unbind_channel_check_hw_state = nvgpu_tsg_unbind_channel_hw_state_check,
.unbind_channel_check_hw_next = gk20a_tsg_unbind_channel_check_hw_next, .unbind_channel_check_hw_next = gk20a_tsg_unbind_channel_check_hw_next,
.unbind_channel_check_ctx_reload = nvgpu_tsg_unbind_channel_check_ctx_reload, .unbind_channel_check_ctx_reload = nvgpu_tsg_unbind_channel_ctx_reload_check,
.unbind_channel_check_eng_faulted = NULL, .unbind_channel_check_eng_faulted = NULL,
#ifdef CONFIG_NVGPU_KERNEL_MODE_SUBMIT #ifdef CONFIG_NVGPU_KERNEL_MODE_SUBMIT
.check_ctxsw_timeout = nvgpu_tsg_check_ctxsw_timeout, .check_ctxsw_timeout = nvgpu_tsg_check_ctxsw_timeout,

4
drivers/gpu/nvgpu/hal/init/hal_gv11b.c
View File

@@ -1032,9 +1032,9 @@ static const struct gops_tsg gv11b_ops_tsg = {
.bind_channel = NULL, .bind_channel = NULL,
.bind_channel_eng_method_buffers = gv11b_tsg_bind_channel_eng_method_buffers, .bind_channel_eng_method_buffers = gv11b_tsg_bind_channel_eng_method_buffers,
.unbind_channel = NULL, .unbind_channel = NULL,
.unbind_channel_check_hw_state = nvgpu_tsg_unbind_channel_check_hw_state, .unbind_channel_check_hw_state = nvgpu_tsg_unbind_channel_hw_state_check,
.unbind_channel_check_hw_next = gk20a_tsg_unbind_channel_check_hw_next, .unbind_channel_check_hw_next = gk20a_tsg_unbind_channel_check_hw_next,
.unbind_channel_check_ctx_reload = nvgpu_tsg_unbind_channel_check_ctx_reload, .unbind_channel_check_ctx_reload = nvgpu_tsg_unbind_channel_ctx_reload_check,
.unbind_channel_check_eng_faulted = gv11b_tsg_unbind_channel_check_eng_faulted, .unbind_channel_check_eng_faulted = gv11b_tsg_unbind_channel_check_eng_faulted,
#ifdef CONFIG_NVGPU_KERNEL_MODE_SUBMIT #ifdef CONFIG_NVGPU_KERNEL_MODE_SUBMIT
.check_ctxsw_timeout = nvgpu_tsg_check_ctxsw_timeout, .check_ctxsw_timeout = nvgpu_tsg_check_ctxsw_timeout,

4
drivers/gpu/nvgpu/hal/init/hal_tu104.c
View File

@@ -1087,9 +1087,9 @@ static const struct gops_tsg tu104_ops_tsg = {
.bind_channel = NULL, .bind_channel = NULL,
.bind_channel_eng_method_buffers = gv11b_tsg_bind_channel_eng_method_buffers, .bind_channel_eng_method_buffers = gv11b_tsg_bind_channel_eng_method_buffers,
.unbind_channel = NULL, .unbind_channel = NULL,
.unbind_channel_check_hw_state = nvgpu_tsg_unbind_channel_check_hw_state, .unbind_channel_check_hw_state = nvgpu_tsg_unbind_channel_hw_state_check,
.unbind_channel_check_hw_next = gk20a_tsg_unbind_channel_check_hw_next, .unbind_channel_check_hw_next = gk20a_tsg_unbind_channel_check_hw_next,
.unbind_channel_check_ctx_reload = nvgpu_tsg_unbind_channel_check_ctx_reload, .unbind_channel_check_ctx_reload = nvgpu_tsg_unbind_channel_ctx_reload_check,
.unbind_channel_check_eng_faulted = gv11b_tsg_unbind_channel_check_eng_faulted, .unbind_channel_check_eng_faulted = gv11b_tsg_unbind_channel_check_eng_faulted,
#ifdef CONFIG_NVGPU_KERNEL_MODE_SUBMIT #ifdef CONFIG_NVGPU_KERNEL_MODE_SUBMIT
.check_ctxsw_timeout = nvgpu_tsg_check_ctxsw_timeout, .check_ctxsw_timeout = nvgpu_tsg_check_ctxsw_timeout,

2
drivers/gpu/nvgpu/include/nvgpu/channel.h
View File

@@ -158,7 +158,7 @@ struct gpfifo_desc {
/** /**
* Structure abstracting H/W state for channel. * Structure abstracting H/W state for channel.
* Used when unbinding a channel from TSG. * Used when unbinding a channel from TSG.
* See #nvgpu_tsg_unbind_channel_check_hw_state. * See #nvgpu_tsg_unbind_channel_hw_state_check.
*/ */
struct nvgpu_channel_hw_state { struct nvgpu_channel_hw_state {
/** Channel scheduling is enabled. */ /** Channel scheduling is enabled. */

4
drivers/gpu/nvgpu/include/nvgpu/tsg.h
View File

@@ -488,7 +488,7 @@ int nvgpu_tsg_unbind_channel(struct nvgpu_tsg *tsg, struct nvgpu_channel *ch,
* @return 0 in case of success and < 0 in case of failure. * @return 0 in case of success and < 0 in case of failure.
* @retval -EINVAL if next bit is set in hw_state. * @retval -EINVAL if next bit is set in hw_state.
*/ */
int nvgpu_tsg_unbind_channel_check_hw_state(struct nvgpu_tsg *tsg, int nvgpu_tsg_unbind_channel_hw_state_check(struct nvgpu_tsg *tsg,
struct nvgpu_channel *ch); struct nvgpu_channel *ch);
/** /**
@@ -504,7 +504,7 @@ int nvgpu_tsg_unbind_channel_check_hw_state(struct nvgpu_tsg *tsg,
* @note If there is only one channel in this TSG then function will not find * @note If there is only one channel in this TSG then function will not find
* another channel to force ctx reload. * another channel to force ctx reload.
*/ */
void nvgpu_tsg_unbind_channel_check_ctx_reload(struct nvgpu_tsg *tsg, void nvgpu_tsg_unbind_channel_ctx_reload_check(struct nvgpu_tsg *tsg,
struct nvgpu_channel *ch, struct nvgpu_channel *ch,
struct nvgpu_channel_hw_state *hw_state); struct nvgpu_channel_hw_state *hw_state);

4
libs/dgpu/libnvgpu-drv-dgpu_safe.export
View File

@@ -702,8 +702,8 @@ nvgpu_tsg_set_ctx_mmu_error
nvgpu_tsg_set_error_notifier nvgpu_tsg_set_error_notifier
nvgpu_tsg_setup_sw nvgpu_tsg_setup_sw
nvgpu_tsg_unbind_channel nvgpu_tsg_unbind_channel
nvgpu_tsg_unbind_channel_check_hw_state nvgpu_tsg_unbind_channel_hw_state_check
nvgpu_tsg_unbind_channel_check_ctx_reload nvgpu_tsg_unbind_channel_ctx_reload_check
nvgpu_set_bit nvgpu_set_bit
nvgpu_set_enabled nvgpu_set_enabled
nvgpu_set_errata nvgpu_set_errata

4
libs/igpu/libnvgpu-drv-igpu_safe.export
View File

@@ -722,8 +722,8 @@ nvgpu_tsg_set_ctx_mmu_error
nvgpu_tsg_set_error_notifier nvgpu_tsg_set_error_notifier
nvgpu_tsg_setup_sw nvgpu_tsg_setup_sw
nvgpu_tsg_unbind_channel nvgpu_tsg_unbind_channel
nvgpu_tsg_unbind_channel_check_hw_state nvgpu_tsg_unbind_channel_hw_state_check
nvgpu_tsg_unbind_channel_check_ctx_reload nvgpu_tsg_unbind_channel_ctx_reload_check
nvgpu_set_bit nvgpu_set_bit
nvgpu_set_enabled nvgpu_set_enabled
nvgpu_set_errata nvgpu_set_errata

4
userspace/units/fifo/tsg/nvgpu-tsg.c
View File

@@ -840,7 +840,7 @@ int test_tsg_unbind_channel_check_hw_state(struct unit_module *m,
branches & F_TSG_UNBIND_CHANNEL_CHECK_HW_ENG_FAULTED ? branches & F_TSG_UNBIND_CHANNEL_CHECK_HW_ENG_FAULTED ?
gops.tsg.unbind_channel_check_eng_faulted : NULL; gops.tsg.unbind_channel_check_eng_faulted : NULL;
err = nvgpu_tsg_unbind_channel_check_hw_state(tsg, ch); err = nvgpu_tsg_unbind_channel_hw_state_check(tsg, ch);
if (branches & F_TSG_UNBIND_CHANNEL_CHECK_HW_NEXT) { if (branches & F_TSG_UNBIND_CHANNEL_CHECK_HW_NEXT) {
unit_assert(err != 0, goto done); unit_assert(err != 0, goto done);
@@ -1055,7 +1055,7 @@ int test_tsg_unbind_channel_check_ctx_reload(struct unit_module *m,
goto done); goto done);
} }
nvgpu_tsg_unbind_channel_check_ctx_reload(tsg, chA, &hw_state); nvgpu_tsg_unbind_channel_ctx_reload_check(tsg, chA, &hw_state);
if ((branches & F_UNBIND_CHANNEL_CHECK_CTX_RELOAD_SET) && if ((branches & F_UNBIND_CHANNEL_CHECK_CTX_RELOAD_SET) &&
(branches & F_UNBIND_CHANNEL_CHECK_CTX_RELOAD_CHID_MATCH)) { (branches & F_UNBIND_CHANNEL_CHECK_CTX_RELOAD_CHID_MATCH)) {

10
userspace/units/fifo/tsg/nvgpu-tsg.h
View File

@@ -201,18 +201,18 @@ int test_tsg_release(struct unit_module *m,
* *
* Test Type: Feature * Test Type: Feature
* *
* Targets: nvgpu_tsg_unbind_channel_check_hw_state, gk20a_tsg_unbind_channel_check_hw_next * Targets: nvgpu_tsg_unbind_channel_hw_state_check, gk20a_tsg_unbind_channel_check_hw_next
* *
* Input: test_fifo_init_support() run for this GPU * Input: test_fifo_init_support() run for this GPU
* *
* Steps: * Steps:
* - Check valid cases for nvgpu_tsg_unbind_channel_check_hw_state: * - Check valid cases for nvgpu_tsg_unbind_channel_hw_state_check:
* - hw_state.next is not set (as per g->ops.channel.read_state). * - hw_state.next is not set (as per g->ops.channel.read_state).
* - Check that g->ops.tsg.unbind_channel_check_ctx_reload is called * - Check that g->ops.tsg.unbind_channel_check_ctx_reload is called
* when defined (using a stub). * when defined (using a stub).
* - Check that g->ops.tsg.unbind_channel_check_eng_faulted is called * - Check that g->ops.tsg.unbind_channel_check_eng_faulted is called
* when defined (using a stub). * when defined (using a stub).
* - Check failure cases in nvgpu_tsg_unbind_channel_check_hw_state: * - Check failure cases in nvgpu_tsg_unbind_channel_hw_state_check:
* - Case where hw_state.next is set (by stubbing g->ops.channel.read_state). * - Case where hw_state.next is set (by stubbing g->ops.channel.read_state).
* *
* Output: Returns PASS if all branches gave expected results. FAIL otherwise. * Output: Returns PASS if all branches gave expected results. FAIL otherwise.
@@ -261,12 +261,12 @@ int test_tsg_sm_error_state_set_get(struct unit_module *m,
* *
* Test Type: Feature * Test Type: Feature
* *
* Targets: nvgpu_tsg_unbind_channel_check_ctx_reload * Targets: nvgpu_tsg_unbind_channel_ctx_reload_check
* *
* Input: test_fifo_init_support() run for this GPU * Input: test_fifo_init_support() run for this GPU
* *
* Steps: * Steps:
* - Check valid cases for nvgpu_tsg_unbind_channel_check_ctx_reload: * - Check valid cases for nvgpu_tsg_unbind_channel_ctx_reload_check:
* - hw_state.ctx_reload is not set (nothing to do). * - hw_state.ctx_reload is not set (nothing to do).
* - hw_state.ctx_reload is set: * - hw_state.ctx_reload is set:
* - Check that what another is bound to TSG, g->ops.channel.force_ctx_reload * - Check that what another is bound to TSG, g->ops.channel.force_ctx_reload