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gpu: nvgpu: common: MISRA rule 15.6 fixes

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MISRA rule 15.6 requires that all if/else/loop blocks should be enclosed
by brackets. This patch adds brackets to single line if/else/loop blocks
in the common directory.

JIRA NVGPU-775

Change-Id: I0dfb38dbf256d49bc0391d889d9fbe5e21da5641
Signed-off-by: Adeel Raza <araza@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2011655
Reviewed-by: svc-misra-checker <svc-misra-checker@nvidia.com>
Reviewed-by: Scott Long <scottl@nvidia.com>
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: Alex Waterman <alexw@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
This commit is contained in:
Adeel Raza
2019-02-04 13:45:38 -08:00
committed by mobile promotions
parent 254253732c
commit d828e013db
10 changed files with 180 additions and 94 deletions
Download Patch File Download Diff File Expand all files Collapse all files

9
drivers/gpu/nvgpu/common/sync/syncpt_cmdbuf_gk20a.c
View File

@@ -1,7 +1,7 @@
/*
* GK20A syncpt cmdbuf
*
* Copyright (c) 2018, NVIDIA CORPORATION. All rights reserved.
* Copyright (c) 2018-2019, NVIDIA CORPORATION. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
@@ -85,10 +85,11 @@ void gk20a_add_syncpt_incr_cmd(struct gk20a *g,
u32 gk20a_get_syncpt_incr_cmd_size(bool wfi_cmd)
{
if (wfi_cmd)
if (wfi_cmd) {
return 8U;
else
} else {
return 6U;
}
}
void gk20a_free_syncpt_buf(struct channel_gk20a *c,
@@ -101,4 +102,4 @@ int gk20a_alloc_syncpt_buf(struct channel_gk20a *c,
u32 syncpt_id, struct nvgpu_mem *syncpt_buf)
{
return 0;
}
}

11
drivers/gpu/nvgpu/common/sync/syncpt_cmdbuf_gv11b.c
View File

@@ -1,7 +1,7 @@
/*
* GV11B syncpt cmdbuf
*
* Copyright (c) 2018, NVIDIA CORPORATION. All rights reserved.
* Copyright (c) 2018-2019, NVIDIA CORPORATION. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
@@ -37,8 +37,9 @@ static int set_syncpt_ro_map_gpu_va_locked(struct vm_gk20a *vm)
{
struct gk20a *g = gk20a_from_vm(vm);
if (vm->syncpt_ro_map_gpu_va)
if (vm->syncpt_ro_map_gpu_va) {
return 0;
}
vm->syncpt_ro_map_gpu_va = nvgpu_gmmu_map(vm,
&g->syncpt_mem, g->syncpt_unit_size,
@@ -68,8 +69,9 @@ int gv11b_alloc_syncpt_buf(struct channel_gk20a *c,
nvgpu_mutex_acquire(&c->vm->syncpt_ro_map_lock);
err = set_syncpt_ro_map_gpu_va_locked(c->vm);
nvgpu_mutex_release(&c->vm->syncpt_ro_map_lock);
if (err != 0)
if (err != 0) {
return err;
}
nr_pages = DIV_ROUND_UP(g->syncpt_size, PAGE_SIZE);
nvgpu_mem_create_from_phys(g, syncpt_buf,
@@ -104,8 +106,9 @@ int gv11b_get_sync_ro_map(struct vm_gk20a *vm,
nvgpu_mutex_acquire(&vm->syncpt_ro_map_lock);
err = set_syncpt_ro_map_gpu_va_locked(vm);
nvgpu_mutex_release(&vm->syncpt_ro_map_lock);
if (err != 0)
if (err != 0) {
return err;
}
*base_gpuva = vm->syncpt_ro_map_gpu_va;
*sync_size = g->syncpt_size;