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gpu: nvgpu: Add Ctrl API to read SM error state
Expose IOCTL to Ctrl node to read Single SM error under NVGPU_GPU_IOCTL_READ_SINGLE_SM_ERROR_STATE bug 200412642 JIRA NVGPU-700 Change-Id: I3cbcf4d7f23a53dbd2350b38a5e259559d5fd3af Signed-off-by: Vinod G <vinodg@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1728931 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
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@@ -864,6 +864,38 @@ struct nvgpu_gpu_set_deterministic_opts_args {
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__u64 channels; /* in */
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};
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/*
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* This struct helps to report the SM error state of a single SM.
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* This acts upon the currently resident GR context.
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* Global Error status register
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* Warp Error status register
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* Warp Error status register PC
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* Global Error status register Report Mask
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* Warp Error status register Report Mask
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*/
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struct nvgpu_gpu_sm_error_state_record {
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__u32 global_esr;
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__u32 warp_esr;
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__u64 warp_esr_pc;
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__u32 global_esr_report_mask;
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__u32 warp_esr_report_mask;
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};
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/*
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* This struct helps to read the SM error state.
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*/
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struct nvgpu_gpu_read_single_sm_error_state_args {
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/* Valid SM ID */
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__u32 sm_id;
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__u32 reserved;
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/*
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* This is pointer to the struct nvgpu_gpu_sm_error_state_record
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*/
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__u64 record_mem;
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/* size of the record size to read */
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__u64 record_size;
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};
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#define NVGPU_GPU_IOCTL_ZCULL_GET_CTX_SIZE \
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_IOR(NVGPU_GPU_IOCTL_MAGIC, 1, struct nvgpu_gpu_zcull_get_ctx_size_args)
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#define NVGPU_GPU_IOCTL_ZCULL_GET_INFO \
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@@ -949,8 +981,11 @@ struct nvgpu_gpu_set_deterministic_opts_args {
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#define NVGPU_GPU_IOCTL_SET_DETERMINISTIC_OPTS \
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_IOWR(NVGPU_GPU_IOCTL_MAGIC, 40, \
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struct nvgpu_gpu_set_deterministic_opts_args)
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#define NVGPU_GPU_IOCTL_READ_SINGLE_SM_ERROR_STATE \
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_IOWR(NVGPU_GPU_IOCTL_MAGIC, 41, \
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struct nvgpu_gpu_read_single_sm_error_state_args)
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#define NVGPU_GPU_IOCTL_LAST \
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_IOC_NR(NVGPU_GPU_IOCTL_SET_DETERMINISTIC_OPTS)
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_IOC_NR(NVGPU_GPU_IOCTL_READ_SINGLE_SM_ERROR_STATE)
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#define NVGPU_GPU_IOCTL_MAX_ARG_SIZE \
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sizeof(struct nvgpu_gpu_get_cpu_time_correlation_info_args)
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