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gpu: nvgpu: support non-secure boot

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For non-secure FALCON boot support, by-pass
MMU check.

Bug 1524197

Change-Id: I735c10a1ea50357c1ea2d5514c73477e76db7e77
Signed-off-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
Reviewed-on: http://git-master/r/424005
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Supriya Sharatkumar <ssharatkumar@nvidia.com>
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
This commit is contained in:
Seshendra Gadagottu
2014-06-16 20:28:45 -07:00
committed by Dan Willemsen
parent 6cd26db477
commit d8e7600ed8
2 changed files with 8 additions and 0 deletions
Download Patch File Download Diff File Expand all files Collapse all files

4
drivers/gpu/nvgpu/gm20b/gr_gm20b.c
View File

@@ -30,6 +30,10 @@ static void gr_gm20b_init_gpc_mmu(struct gk20a *g)
gk20a_dbg_info("initialize gpc mmu"); gk20a_dbg_info("initialize gpc mmu");
/* Bypass MMU check for non-secure boot. For
* secure-boot,this register write has no-effect */
gk20a_writel(g, fb_priv_mmu_phy_secure_r(), 0xffffffff);
temp = gk20a_readl(g, fb_mmu_ctrl_r()); temp = gk20a_readl(g, fb_mmu_ctrl_r());
temp &= gr_gpcs_pri_mmu_ctrl_vm_pg_size_m() | temp &= gr_gpcs_pri_mmu_ctrl_vm_pg_size_m() |
gr_gpcs_pri_mmu_ctrl_use_pdb_big_page_size_m() | gr_gpcs_pri_mmu_ctrl_use_pdb_big_page_size_m() |

4
drivers/gpu/nvgpu/gm20b/hw_fb_gm20b.h
View File

@@ -58,6 +58,10 @@ static inline u32 fb_mmu_ctrl_r(void)
{ {
return 0x00100c80; return 0x00100c80;
} }
static inline u32 fb_priv_mmu_phy_secure_r(void)
{
return 0x00100ce4;
}
static inline u32 fb_mmu_ctrl_vm_pg_size_f(u32 v) static inline u32 fb_mmu_ctrl_vm_pg_size_f(u32 v)
{ {
return (v & 0x1) << 0; return (v & 0x1) << 0;