gpu: nvgpu: support non-secure boot

For non-secure FALCON boot support, by-pass
MMU check.

Bug 1524197

Change-Id: I735c10a1ea50357c1ea2d5514c73477e76db7e77
Signed-off-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
Reviewed-on: http://git-master/r/424005
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Supriya Sharatkumar <ssharatkumar@nvidia.com>
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>

drivers/gpu/nvgpu/gm20b/gr_gm20b.c

@@ -30,6 +30,10 @@ static void gr_gm20b_init_gpc_mmu(struct gk20a *g)
 
 	gk20a_dbg_info("initialize gpc mmu");
 
+	/* Bypass MMU check for non-secure boot. For
+	 * secure-boot,this register write has no-effect */
+	gk20a_writel(g, fb_priv_mmu_phy_secure_r(), 0xffffffff);
+
 	temp = gk20a_readl(g, fb_mmu_ctrl_r());
 	temp &= gr_gpcs_pri_mmu_ctrl_vm_pg_size_m() |
 		gr_gpcs_pri_mmu_ctrl_use_pdb_big_page_size_m() |

drivers/gpu/nvgpu/gm20b/hw_fb_gm20b.h

@@ -58,6 +58,10 @@ static inline u32 fb_mmu_ctrl_r(void)
 {
 	return 0x00100c80;
 }
+static inline u32 fb_priv_mmu_phy_secure_r(void)
+{
+	return 0x00100ce4;
+}
 static inline u32 fb_mmu_ctrl_vm_pg_size_f(u32 v)
 {
 	return (v & 0x1) << 0;