From d8ec4e4e12dc87894647d7cbd9600fbacc1b0852 Mon Sep 17 00:00:00 2001 From: Deepak Nibade Date: Fri, 12 Apr 2019 18:53:05 +0530 Subject: [PATCH] gpu: nvgpu: move zcull size initialization to falcon unit Move zcull size initialization to hal.gr.zcull unit. This removes zcull dependency on falcon unit Add new variable zcull_image_size to gr_gk20a.ctx_vars struct Pass the size to nvgpu_gr_zcull_init()/vgpu_gr_init_gr_zcull() as parameter to initialize zcull info Jira NVGPU-3112 Change-Id: I54d966073dad658b4aad3a529f44c0478208b10c Signed-off-by: Deepak Nibade Reviewed-on: https://git-master.nvidia.com/r/2098507 Reviewed-by: mobile promotions Tested-by: mobile promotions --- drivers/gpu/nvgpu/common/gr/gr.c | 2 +- drivers/gpu/nvgpu/common/gr/zcull.c | 5 +++- drivers/gpu/nvgpu/common/vgpu/gr/gr_vgpu.c | 11 +++++--- drivers/gpu/nvgpu/gk20a/gr_gk20a.h | 4 +++ .../gpu/nvgpu/hal/gr/falcon/gr_falcon_gm20b.c | 8 ++++++ drivers/gpu/nvgpu/hal/gr/zcull/zcull_gm20b.c | 25 ------------------- drivers/gpu/nvgpu/include/nvgpu/gr/zcull.h | 3 ++- 7 files changed, 26 insertions(+), 32 deletions(-) diff --git a/drivers/gpu/nvgpu/common/gr/gr.c b/drivers/gpu/nvgpu/common/gr/gr.c index 0da1e19ae..74f07ba69 100644 --- a/drivers/gpu/nvgpu/common/gr/gr.c +++ b/drivers/gpu/nvgpu/common/gr/gr.c @@ -411,7 +411,7 @@ static int gr_init_setup_sw(struct gk20a *g) goto clean_up; } - err = nvgpu_gr_zcull_init(g, &gr->zcull); + err = nvgpu_gr_zcull_init(g, &gr->zcull, gr->ctx_vars.zcull_image_size); if (err != 0) { goto clean_up; } diff --git a/drivers/gpu/nvgpu/common/gr/zcull.c b/drivers/gpu/nvgpu/common/gr/zcull.c index fb3faccf5..e52b4304a 100644 --- a/drivers/gpu/nvgpu/common/gr/zcull.c +++ b/drivers/gpu/nvgpu/common/gr/zcull.c @@ -30,7 +30,8 @@ #include "zcull_priv.h" -int nvgpu_gr_zcull_init(struct gk20a *g, struct nvgpu_gr_zcull **gr_zcull) +int nvgpu_gr_zcull_init(struct gk20a *g, struct nvgpu_gr_zcull **gr_zcull, + u32 size) { struct nvgpu_gr_config *gr_config = g->gr.config; struct nvgpu_gr_zcull *zcull; @@ -44,6 +45,8 @@ int nvgpu_gr_zcull_init(struct gk20a *g, struct nvgpu_gr_zcull **gr_zcull) zcull->g = g; + zcull->zcull_ctxsw_image_size = size; + zcull->aliquot_width = nvgpu_gr_config_get_tpc_count(gr_config) * 16U; zcull->aliquot_height = 16; diff --git a/drivers/gpu/nvgpu/common/vgpu/gr/gr_vgpu.c b/drivers/gpu/nvgpu/common/vgpu/gr/gr_vgpu.c index f4a55e520..bca3cf30d 100644 --- a/drivers/gpu/nvgpu/common/vgpu/gr/gr_vgpu.c +++ b/drivers/gpu/nvgpu/common/vgpu/gr/gr_vgpu.c @@ -146,8 +146,8 @@ int vgpu_gr_init_ctx_state(struct gk20a *g) return -ENXIO; } - g->gr.zcull->zcull_ctxsw_image_size = priv->constants.zcull_ctx_size; - if (g->gr.zcull->zcull_ctxsw_image_size == 0U) { + g->gr.ctx_vars.zcull_image_size = priv->constants.zcull_ctx_size; + if (g->gr.ctx_vars.zcull_image_size == 0U) { return -ENXIO; } @@ -467,7 +467,8 @@ cleanup: return err; } -static int vgpu_gr_init_gr_zcull(struct gk20a *g, struct gr_gk20a *gr) +static int vgpu_gr_init_gr_zcull(struct gk20a *g, struct gr_gk20a *gr, + u32 size) { nvgpu_log_fn(g, " "); @@ -476,6 +477,8 @@ static int vgpu_gr_init_gr_zcull(struct gk20a *g, struct gr_gk20a *gr) return -ENOMEM; } + gr->zcull->zcull_ctxsw_image_size = size; + return 0; } int vgpu_gr_bind_ctxsw_zcull(struct gk20a *g, struct channel_gk20a *c, @@ -730,7 +733,7 @@ static int vgpu_gr_init_gr_setup_sw(struct gk20a *g) goto clean_up; } - err = vgpu_gr_init_gr_zcull(g, gr); + err = vgpu_gr_init_gr_zcull(g, gr, gr->ctx_vars.zcull_image_size); if (err) { goto clean_up; } diff --git a/drivers/gpu/nvgpu/gk20a/gr_gk20a.h b/drivers/gpu/nvgpu/gk20a/gr_gk20a.h index 81b068f7a..5838a5785 100644 --- a/drivers/gpu/nvgpu/gk20a/gr_gk20a.h +++ b/drivers/gpu/nvgpu/gk20a/gr_gk20a.h @@ -104,8 +104,12 @@ struct gr_gk20a { u32 pm_ctxsw_image_size; u32 preempt_image_size; + + u32 zcull_image_size; + bool force_preemption_gfxp; bool force_preemption_cilp; + bool dump_ctxsw_stats_on_channel_close; } ctx_vars; diff --git a/drivers/gpu/nvgpu/hal/gr/falcon/gr_falcon_gm20b.c b/drivers/gpu/nvgpu/hal/gr/falcon/gr_falcon_gm20b.c index 7af921faf..60e16bc71 100644 --- a/drivers/gpu/nvgpu/hal/gr/falcon/gr_falcon_gm20b.c +++ b/drivers/gpu/nvgpu/hal/gr/falcon/gr_falcon_gm20b.c @@ -684,6 +684,14 @@ int gm20b_gr_falcon_init_ctx_state(struct gk20a *g) "query pm ctx image size failed"); return ret; } + ret = gm20b_gr_falcon_ctrl_ctxsw(g, + NVGPU_GR_FALCON_METHOD_CTXSW_DISCOVER_ZCULL_IMAGE_SIZE, + 0, &g->gr.ctx_vars.zcull_image_size); + if (ret != 0) { + nvgpu_err(g, + "query zcull ctx image size failed"); + return ret; + } } nvgpu_log_fn(g, "done"); diff --git a/drivers/gpu/nvgpu/hal/gr/zcull/zcull_gm20b.c b/drivers/gpu/nvgpu/hal/gr/zcull/zcull_gm20b.c index 989f1464e..233a292e1 100644 --- a/drivers/gpu/nvgpu/hal/gr/zcull/zcull_gm20b.c +++ b/drivers/gpu/nvgpu/hal/gr/zcull/zcull_gm20b.c @@ -26,7 +26,6 @@ #include #include #include -#include #include "common/gr/zcull_priv.h" @@ -34,24 +33,6 @@ #include -static int gm20b_gr_init_zcull_ctxsw_image_size(struct gk20a *g, - struct nvgpu_gr_zcull *gr_zcull) -{ - int ret = 0; - - if (!g->gr.ctx_vars.golden_image_initialized) { - ret = g->ops.gr.falcon.ctrl_ctxsw(g, - NVGPU_GR_FALCON_METHOD_CTXSW_DISCOVER_ZCULL_IMAGE_SIZE, - 0, &gr_zcull->zcull_ctxsw_image_size); - if (ret != 0) { - nvgpu_err(g, - "query zcull ctx image size failed"); - return ret; - } - } - return ret; -} - int gm20b_gr_init_zcull_hw(struct gk20a *g, struct nvgpu_gr_zcull *gr_zcull, struct nvgpu_gr_config *gr_config) @@ -61,17 +42,11 @@ int gm20b_gr_init_zcull_hw(struct gk20a *g, bool floorsweep = false; u32 rcp_conserv; u32 offset; - int ret; gr_zcull->total_aliquots = gr_gpc0_zcull_total_ram_size_num_aliquots_f( nvgpu_readl(g, gr_gpc0_zcull_total_ram_size_r())); - ret = gm20b_gr_init_zcull_ctxsw_image_size(g, gr_zcull); - if (ret != 0) { - return ret; - } - for (gpc_index = 0; gpc_index < nvgpu_gr_config_get_gpc_count(gr_config); gpc_index++) { diff --git a/drivers/gpu/nvgpu/include/nvgpu/gr/zcull.h b/drivers/gpu/nvgpu/include/nvgpu/gr/zcull.h index 83dbf8db6..de117a9b5 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/gr/zcull.h +++ b/drivers/gpu/nvgpu/include/nvgpu/gr/zcull.h @@ -44,7 +44,8 @@ struct nvgpu_gr_zcull_info { u32 subregion_count; }; -int nvgpu_gr_zcull_init(struct gk20a *g, struct nvgpu_gr_zcull **gr_zcull); +int nvgpu_gr_zcull_init(struct gk20a *g, struct nvgpu_gr_zcull **gr_zcull, + u32 size); void nvgpu_gr_zcull_deinit(struct gk20a *g, struct nvgpu_gr_zcull *gr_zcull); u32 nvgpu_gr_get_ctxsw_zcull_size(struct gk20a *g,