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gpu: nvgpu: update .read_state to use runlist_id and chid

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Moving to use IDs rather than struct makes it reusable on server side.

Jira GVSCI-15770

Change-Id: Ia5e30ebb0e8092b9cdc4c3f3cd524f585fd4b410
Signed-off-by: Richard Zhao <rizhao@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2863437
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-cert <svc-mobile-cert@nvidia.com>
Reviewed-by: Dinesh T <dt@nvidia.com>
GVS: Gerrit_Virtual_Submit <buildbot_gerritrpt@nvidia.com>
This commit is contained in:
Richard Zhao
2023-02-14 14:59:31 -08:00
committed by mobile promotions
parent 2ff110f722
commit d9c8d317f0
14 changed files with 39 additions and 45 deletions
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5
userspace/units/fifo/channel/gk20a/nvgpu-channel-gk20a.c
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@@ -1,5 +1,5 @@
/*
* Copyright (c) 2019-2020, NVIDIA CORPORATION. All rights reserved.
* Copyright (c) 2019-2023, NVIDIA CORPORATION. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
@@ -195,7 +195,8 @@ int test_gk20a_channel_read_state(struct unit_module *m,
nvgpu_writel(g, ccsr_channel_r(ch->chid), v);
gk20a_channel_read_state(g, ch, &state);
gk20a_channel_read_state(g, ch->runlist->id, ch->chid,
&state);
unit_assert(state.next == next, goto done);
unit_assert(state.enabled == enabled, goto done);

4
userspace/units/fifo/channel/gv11b/nvgpu-channel-gv11b.c
View File

@@ -1,5 +1,5 @@
/*
* Copyright (c) 2019-2022, NVIDIA CORPORATION. All rights reserved.
* Copyright (c) 2019-2023, NVIDIA CORPORATION. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
@@ -163,7 +163,7 @@ int test_gv11b_channel_read_state(struct unit_module *m,
nvgpu_writel(g, ccsr_channel_r(ch->chid), v);
gv11b_channel_read_state(g, ch, &state);
gv11b_channel_read_state(g, ch->runlist->id, ch->chid, &state);
unit_assert(state.eng_faulted == eng_faulted, goto done);
}

6
userspace/units/fifo/channel/nvgpu-channel.c
View File

@@ -1,5 +1,5 @@
/*
* Copyright (c) 2019-2022, NVIDIA CORPORATION. All rights reserved.
* Copyright (c) 2019-2023, NVIDIA CORPORATION. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
@@ -1671,10 +1671,10 @@ static const char *f_channel_debug_dump[] = {
"info_alloc_fail",
};
static void stub_channel_read_state(struct gk20a *g, struct nvgpu_channel *ch,
static void stub_channel_read_state(struct gk20a *g, u32 runlist_id, u32 chid,
struct nvgpu_channel_hw_state *state)
{
stub[0].chid = ch->chid;
stub[0].chid = chid;
}
static void stub_ramfc_capture_ram_dump(struct gk20a *g,

6
userspace/units/fifo/tsg/nvgpu-tsg.c
View File

@@ -1,5 +1,5 @@
/*
* Copyright (c) 2018-2022, NVIDIA CORPORATION. All rights reserved.
* Copyright (c) 2018-2023, NVIDIA CORPORATION. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
@@ -775,13 +775,13 @@ static const char *f_tsg_unbind_channel_check_hw[] = {
};
static void stub_channel_read_state_NEXT(struct gk20a *g,
struct nvgpu_channel *ch, struct nvgpu_channel_hw_state *state)
u32 runlist_id, u32 chid, struct nvgpu_channel_hw_state *state)
{
state->next = true;
}
static void stub_channel_read_state_NEXT_CLR(struct gk20a *g,
struct nvgpu_channel *ch, struct nvgpu_channel_hw_state *state)
u32 runlist_id, u32 chid, struct nvgpu_channel_hw_state *state)
{
state->next = false;
}