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gpu: nvgpu: Move programming FB phys access to FB

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FB physical access register for simulation was programmed in GR
implementation. Move it to FB where it belongs.

JIRA NVGPU-714

Change-Id: Ic5146a61c7d45eadffdb4f3b6b08906bfcdbc224
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1772915
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
This commit is contained in:
Terje Bergstrom
2018-07-06 10:03:31 -07:00
committed by mobile promotions
parent ad3b170f43
commit da03aa7825
4 changed files with 12 additions and 10 deletions
Download Patch File Download Diff File Expand all files Collapse all files

6
drivers/gpu/nvgpu/gm20b/fb_gm20b.c
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@@ -42,6 +42,12 @@ void fb_gm20b_init_fs_state(struct gk20a *g)
gk20a_writel(g, fb_fbhub_num_active_ltcs_r(), gk20a_writel(g, fb_fbhub_num_active_ltcs_r(),
g->ltc_count); g->ltc_count);
if (!nvgpu_is_enabled(g, NVGPU_SEC_PRIVSECURITY)) {
/* Bypass MMU check for non-secure boot. For
* secure-boot,this register write has no-effect */
gk20a_writel(g, fb_priv_mmu_phy_secure_r(), 0xffffffffU);
}
} }
void gm20b_fb_set_mmu_page_size(struct gk20a *g) void gm20b_fb_set_mmu_page_size(struct gk20a *g)

5
drivers/gpu/nvgpu/gm20b/gr_gm20b.c
View File

@@ -49,11 +49,6 @@ void gr_gm20b_init_gpc_mmu(struct gk20a *g)
nvgpu_log_info(g, "initialize gpc mmu"); nvgpu_log_info(g, "initialize gpc mmu");
if (!nvgpu_is_enabled(g, NVGPU_SEC_PRIVSECURITY)) {
/* Bypass MMU check for non-secure boot. For
* secure-boot,this register write has no-effect */
gk20a_writel(g, fb_priv_mmu_phy_secure_r(), 0xffffffff);
}
temp = gk20a_readl(g, fb_mmu_ctrl_r()); temp = gk20a_readl(g, fb_mmu_ctrl_r());
temp &= gr_gpcs_pri_mmu_ctrl_vm_pg_size_m() | temp &= gr_gpcs_pri_mmu_ctrl_vm_pg_size_m() |
gr_gpcs_pri_mmu_ctrl_use_pdb_big_page_size_m() | gr_gpcs_pri_mmu_ctrl_use_pdb_big_page_size_m() |

6
drivers/gpu/nvgpu/gv11b/fb_gv11b.c
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@@ -68,6 +68,12 @@ void gv11b_fb_init_fs_state(struct gk20a *g)
nvgpu_log(g, gpu_dbg_info, "mmu active ltcs %u", nvgpu_log(g, gpu_dbg_info, "mmu active ltcs %u",
fb_mmu_num_active_ltcs_count_v( fb_mmu_num_active_ltcs_count_v(
gk20a_readl(g, fb_mmu_num_active_ltcs_r()))); gk20a_readl(g, fb_mmu_num_active_ltcs_r())));
if (!nvgpu_is_enabled(g, NVGPU_SEC_PRIVSECURITY)) {
/* Bypass MMU check for non-secure boot. For
* secure-boot,this register write has no-effect */
gk20a_writel(g, fb_priv_mmu_phy_secure_r(), 0xffffffffU);
}
} }
void gv11b_fb_init_cbc(struct gk20a *g, struct gr_gk20a *gr) void gv11b_fb_init_cbc(struct gk20a *g, struct gr_gk20a *gr)

5
drivers/gpu/nvgpu/gv11b/gr_gv11b.c
View File

@@ -4248,11 +4248,6 @@ void gr_gv11b_init_gpc_mmu(struct gk20a *g)
nvgpu_log_info(g, "initialize gpc mmu"); nvgpu_log_info(g, "initialize gpc mmu");
if (!nvgpu_is_enabled(g, NVGPU_SEC_PRIVSECURITY)) {
/* Bypass MMU check for non-secure boot. For
* secure-boot,this register write has no-effect */
gk20a_writel(g, fb_priv_mmu_phy_secure_r(), 0xffffffff);
}
temp = gk20a_readl(g, fb_mmu_ctrl_r()); temp = gk20a_readl(g, fb_mmu_ctrl_r());
temp &= gr_gpcs_pri_mmu_ctrl_vm_pg_size_m() | temp &= gr_gpcs_pri_mmu_ctrl_vm_pg_size_m() |
gr_gpcs_pri_mmu_ctrl_use_pdb_big_page_size_m() | gr_gpcs_pri_mmu_ctrl_use_pdb_big_page_size_m() |