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gpu: nvgpu: ga10b: LSPMU interrupt update

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Enable/disable LSPMU interrupt in MC, as required LSPMU
interrupts are configured as part of LSPMU ucode init and
don't need any additional PMU IRQ register to set/clear as
part of GPU power-on/off sequence.

Bug 3681561

Change-Id: Ifb47bc9cc83e16e46649b0eef5f257acb02f302c
Signed-off-by: mkumbar <mkumbar@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2740623
Reviewed-by: svcacv <svcacv@nvidia.com>
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
GVS: Gerrit_Virtual_Submit
This commit is contained in:
mkumbar
2022-07-04 18:58:20 +05:30
committed by mobile promotions
parent e89553fe62
commit da632aa173
1 changed files with 2 additions and 15 deletions
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17
drivers/gpu/nvgpu/hal/pmu/pmu_ga10b.c
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@@ -404,18 +404,9 @@ bool ga10b_pmu_is_interrupted(struct nvgpu_pmu *pmu)
#endif
/*
* GA10B PMU IRQ registers are not accessible when NVRISCV PRIV lockdown is
* engaged, so need to skip modifying/configuring IRQ registers.
*
* HAL checks for PRIV lockdown and if enabled then just enable PMU interrupt
* from MC, if not enabled then follows legacy chip method to configure
* the PMU interrupt.
*
* Interrupts required for LS-PMU are configured by LS-PMU ucode as part of
* LS-PMU init code.
*
* Legacy chip path helps to configure interrupt required of non LS-PMU ucode
* or power-off path to clear interrupt.
* LS-PMU init code, so just enable/disable PMU interrupt from MC.
*
*/
void ga10b_pmu_enable_irq(struct nvgpu_pmu *pmu, bool enable)
@@ -424,13 +415,9 @@ void ga10b_pmu_enable_irq(struct nvgpu_pmu *pmu, bool enable)
nvgpu_log_fn(g, " ");
if (g->ops.falcon.is_priv_lockdown(pmu->flcn)) {
nvgpu_cic_mon_intr_stall_unit_config(g,
nvgpu_cic_mon_intr_stall_unit_config(g,
NVGPU_CIC_INTR_UNIT_PMU,
enable);
} else {
gv11b_pmu_enable_irq(pmu, enable);
}
}
static int ga10b_pmu_handle_ecc(struct gk20a *g)