From dae284c74bcc08b1337aef7fc073c33b21d5892c Mon Sep 17 00:00:00 2001 From: Tejal Kudav Date: Fri, 8 Apr 2022 05:44:30 +0000 Subject: [PATCH] gpu: nvgpu: Disable GR functional intrs on safety Disable below interrupts on safety as they do not report any error condition and are not used by CUDA and Graphics(VKSC) on safety build. Signoff from CUDA and VKSC is on Bug https://nvbugs/3588603 1. NV_PGRAPH_INTR_NOTIFY: This intr is set when the Notification style is WRITE_THEN_AWAKEN. 2. NV_PGRAPH_INTR_SEMAPHORE: This is set when a 3d class sempahore is released as the result ofa SetSemaphoreD method, when the AwakenEnable field is TRUE. 3. NV_PGRAPH_INTR_BUFFER_NOTIFY: This bit is set when a Mem2mem DMA completes and the LaunchDma method specifies the interrupt type as INTERRUPT 4. NV_PGRAPH_INTR_DEBUG_METHODS: This is debug feature and not used on QNX safety Bug 3588603 JIRA NVGPU-8166 Change-Id: I6d07dfd2857ac047fac4599421600d364251df76 Signed-off-by: Tejal Kudav Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2694363 Tested-by: mobile promotions Reviewed-by: mobile promotions --- drivers/gpu/nvgpu/common/gr/gr_intr.c | 5 +- drivers/gpu/nvgpu/common/gr/gr_intr_priv.h | 28 ++++++----- .../nvgpu/hal/gr/intr/gr_intr_ga100_fusa.c | 49 ++++++++++--------- .../nvgpu/hal/gr/intr/gr_intr_ga10b_fusa.c | 27 +++++----- .../nvgpu/hal/gr/intr/gr_intr_gm20b_fusa.c | 2 + 5 files changed, 63 insertions(+), 48 deletions(-) diff --git a/drivers/gpu/nvgpu/common/gr/gr_intr.c b/drivers/gpu/nvgpu/common/gr/gr_intr.c index ac7e8d4d2..1aafad54a 100644 --- a/drivers/gpu/nvgpu/common/gr/gr_intr.c +++ b/drivers/gpu/nvgpu/common/gr/gr_intr.c @@ -851,6 +851,7 @@ static u32 gr_intr_handle_error_interrupts(struct gk20a *g, return do_reset; } +#ifdef CONFIG_NVGPU_NON_FUSA static void gr_intr_handle_pending_interrupts(struct gk20a *g, u32 *clear_intr, struct nvgpu_gr_intr_info *intr_info, @@ -882,6 +883,7 @@ static void gr_intr_handle_pending_interrupts(struct gk20a *g, *clear_intr &= ~intr_info->debug_method; } } +#endif static struct nvgpu_tsg *gr_intr_get_channel_from_ctx(struct gk20a *g, u32 gr_intr, u32 *chid, @@ -972,9 +974,10 @@ int nvgpu_gr_intr_stall_isr(struct gk20a *g) &isr_data); } +#ifdef CONFIG_NVGPU_NON_FUSA gr_intr_handle_pending_interrupts(g, &clear_intr, &intr_info, &isr_data); - +#endif need_reset |= gr_intr_handle_illegal_interrupts(g, &clear_intr, &intr_info, &isr_data); diff --git a/drivers/gpu/nvgpu/common/gr/gr_intr_priv.h b/drivers/gpu/nvgpu/common/gr/gr_intr_priv.h index a3efbd9a2..f6098bf58 100644 --- a/drivers/gpu/nvgpu/common/gr/gr_intr_priv.h +++ b/drivers/gpu/nvgpu/common/gr/gr_intr_priv.h @@ -42,6 +42,7 @@ struct nvgpu_channel; * This structure maintains information on pending GR engine interrupts. */ struct nvgpu_gr_intr_info { +#ifdef CONFIG_NVGPU_NON_FUSA /** * This value is set in case notification interrupt is pending. * Same value is used to clear the interrupt. @@ -52,6 +53,20 @@ struct nvgpu_gr_intr_info { * Same value is used to clear the interrupt. */ u32 semaphore; + /* + * This value is set when the FE receives a valid method and it + * matches with the value configured in PRI_FE_DEBUG_METHOD_* pri + * registers; In case of a match, FE proceeds to drop that method. + * This provides a way to the SW to turn off HW decoding of this + * method and convert it to a SW method. + */ + u32 debug_method; + /* + * This value is set on the completion of a LaunchDma method with + * InterruptType field configured to INTERRUPT. + */ + u32 buffer_notify; +#endif /** * This value is set in case illegal notify interrupt is pending. * Same value is used to clear the interrupt. @@ -87,19 +102,6 @@ struct nvgpu_gr_intr_info { * Same value is used to clear the interrupt. */ u32 exception; - /* - * This value is set when the FE receives a valid method and it - * matches with the value configured in PRI_FE_DEBUG_METHOD_* pri - * registers; In case of a match, FE proceeds to drop that method. - * This provides a way to the SW to turn off HW decoding of this - * method and convert it to a SW method. - */ - u32 debug_method; - /* - * This value is set on the completion of a LaunchDma method with - * InterruptType field configured to INTERRUPT. - */ - u32 buffer_notify; }; /** diff --git a/drivers/gpu/nvgpu/hal/gr/intr/gr_intr_ga100_fusa.c b/drivers/gpu/nvgpu/hal/gr/intr/gr_intr_ga100_fusa.c index bd3f8c9bf..69a0b888e 100644 --- a/drivers/gpu/nvgpu/hal/gr/intr/gr_intr_ga100_fusa.c +++ b/drivers/gpu/nvgpu/hal/gr/intr/gr_intr_ga100_fusa.c @@ -38,23 +38,25 @@ #include -#define GR_INTR_EN_MASK (\ - gr_intr_en_notify__prod_f() | \ - gr_intr_en_semaphore__prod_f() | \ - gr_intr_en_illegal_method__prod_f() | \ - gr_intr_en_illegal_class__prod_f() | \ - gr_intr_en_illegal_notify__prod_f() | \ - gr_intr_en_debug_method__prod_f() | \ - gr_intr_en_firmware_method__prod_f() | \ - gr_intr_en_buffer_notify__prod_f() | \ - gr_intr_en_fecs_error__prod_f() | \ - gr_intr_en_class_error__prod_f() | \ - gr_intr_en_exception__prod_f() | \ - gr_intr_en_fe_debug_intr__prod_f()) - u32 ga100_gr_intr_enable_mask(struct gk20a *g) { - return GR_INTR_EN_MASK; + u32 mask = +#ifdef CONFIG_NVGPU_NON_FUSA + gr_intr_en_notify__prod_f() | + gr_intr_en_semaphore__prod_f() | + gr_intr_en_buffer_notify__prod_f() | + gr_intr_en_debug_method__prod_f() | +#endif + gr_intr_en_illegal_method__prod_f() | + gr_intr_en_illegal_class__prod_f() | + gr_intr_en_illegal_notify__prod_f() | + gr_intr_en_firmware_method__prod_f() | + gr_intr_en_fecs_error__prod_f() | + gr_intr_en_class_error__prod_f() | + gr_intr_en_exception__prod_f() | + gr_intr_en_fe_debug_intr__prod_f(); + + return mask; } u32 ga100_gr_intr_read_pending_interrupts(struct gk20a *g, @@ -64,6 +66,7 @@ u32 ga100_gr_intr_read_pending_interrupts(struct gk20a *g, (void) memset(intr_info, 0, sizeof(struct nvgpu_gr_intr_info)); +#ifdef CONFIG_NVGPU_NON_FUSA if ((gr_intr & gr_intr_notify_pending_f()) != 0U) { intr_info->notify = gr_intr_notify_pending_f(); } @@ -72,6 +75,14 @@ u32 ga100_gr_intr_read_pending_interrupts(struct gk20a *g, intr_info->semaphore = gr_intr_semaphore_pending_f(); } + if ((gr_intr & gr_intr_buffer_notify_pending_f()) != 0U) { + intr_info->buffer_notify = gr_intr_buffer_notify_pending_f(); + } + + if ((gr_intr & gr_intr_debug_method_pending_f()) != 0U) { + intr_info->debug_method = gr_intr_debug_method_pending_f(); + } +#endif if ((gr_intr & gr_intr_illegal_notify_pending_f()) != 0U) { intr_info->illegal_notify = gr_intr_illegal_notify_pending_f(); } @@ -84,10 +95,6 @@ u32 ga100_gr_intr_read_pending_interrupts(struct gk20a *g, intr_info->illegal_class = gr_intr_illegal_class_pending_f(); } - if ((gr_intr & gr_intr_buffer_notify_pending_f()) != 0U) { - intr_info->buffer_notify = gr_intr_buffer_notify_pending_f(); - } - if ((gr_intr & gr_intr_fecs_error_pending_f()) != 0U) { intr_info->fecs_error = gr_intr_fecs_error_pending_f(); } @@ -96,10 +103,6 @@ u32 ga100_gr_intr_read_pending_interrupts(struct gk20a *g, intr_info->class_error = gr_intr_class_error_pending_f(); } - if ((gr_intr & gr_intr_debug_method_pending_f()) != 0U) { - intr_info->debug_method = gr_intr_debug_method_pending_f(); - } - /* this one happens if someone tries to hit a non-whitelisted * register using set_falcon[4] */ if ((gr_intr & gr_intr_firmware_method_pending_f()) != 0U) { diff --git a/drivers/gpu/nvgpu/hal/gr/intr/gr_intr_ga10b_fusa.c b/drivers/gpu/nvgpu/hal/gr/intr/gr_intr_ga10b_fusa.c index 2e1a756d7..434092296 100644 --- a/drivers/gpu/nvgpu/hal/gr/intr/gr_intr_ga10b_fusa.c +++ b/drivers/gpu/nvgpu/hal/gr/intr/gr_intr_ga10b_fusa.c @@ -43,13 +43,16 @@ static u32 gr_intr_en_mask(void) { - u32 mask = gr_intr_en_notify__prod_f() | + u32 mask = +#ifdef CONFIG_NVGPU_NON_FUSA + gr_intr_en_notify__prod_f() | gr_intr_en_semaphore__prod_f() | + gr_intr_en_debug_method__prod_f() | + gr_intr_en_buffer_notify__prod_f() | +#endif gr_intr_en_illegal_method__prod_f() | gr_intr_en_illegal_notify__prod_f() | - gr_intr_en_debug_method__prod_f() | gr_intr_en_firmware_method__prod_f() | - gr_intr_en_buffer_notify__prod_f() | gr_intr_en_fecs_error__prod_f() | gr_intr_en_class_error__prod_f() | gr_intr_en_exception__prod_f() | @@ -1112,6 +1115,7 @@ u32 ga10b_gr_intr_read_pending_interrupts(struct gk20a *g, (void) memset(intr_info, 0, sizeof(struct nvgpu_gr_intr_info)); +#ifdef CONFIG_NVGPU_NON_FUSA if ((gr_intr & gr_intr_notify_pending_f()) != 0U) { intr_info->notify = gr_intr_notify_pending_f(); } @@ -1120,6 +1124,15 @@ u32 ga10b_gr_intr_read_pending_interrupts(struct gk20a *g, intr_info->semaphore = gr_intr_semaphore_pending_f(); } + if ((gr_intr & gr_intr_buffer_notify_pending_f()) != 0U) { + intr_info->buffer_notify = gr_intr_buffer_notify_pending_f(); + } + + if ((gr_intr & gr_intr_debug_method_pending_f()) != 0U) { + intr_info->debug_method = gr_intr_debug_method_pending_f(); + } +#endif + if ((gr_intr & gr_intr_illegal_notify_pending_f()) != 0U) { intr_info->illegal_notify = gr_intr_illegal_notify_pending_f(); } @@ -1128,10 +1141,6 @@ u32 ga10b_gr_intr_read_pending_interrupts(struct gk20a *g, intr_info->illegal_method = gr_intr_illegal_method_pending_f(); } - if ((gr_intr & gr_intr_buffer_notify_pending_f()) != 0U) { - intr_info->buffer_notify = gr_intr_buffer_notify_pending_f(); - } - if ((gr_intr & gr_intr_fecs_error_pending_f()) != 0U) { intr_info->fecs_error = gr_intr_fecs_error_pending_f(); } @@ -1140,10 +1149,6 @@ u32 ga10b_gr_intr_read_pending_interrupts(struct gk20a *g, intr_info->class_error = gr_intr_class_error_pending_f(); } - if ((gr_intr & gr_intr_debug_method_pending_f()) != 0U) { - intr_info->debug_method = gr_intr_debug_method_pending_f(); - } - /* this one happens if someone tries to hit a non-whitelisted * register using set_falcon[4] */ if ((gr_intr & gr_intr_firmware_method_pending_f()) != 0U) { diff --git a/drivers/gpu/nvgpu/hal/gr/intr/gr_intr_gm20b_fusa.c b/drivers/gpu/nvgpu/hal/gr/intr/gr_intr_gm20b_fusa.c index 42b96b059..c4d75b5e7 100644 --- a/drivers/gpu/nvgpu/hal/gr/intr/gr_intr_gm20b_fusa.c +++ b/drivers/gpu/nvgpu/hal/gr/intr/gr_intr_gm20b_fusa.c @@ -54,6 +54,7 @@ u32 gm20b_gr_intr_read_pending_interrupts(struct gk20a *g, (void) memset(intr_info, 0, sizeof(struct nvgpu_gr_intr_info)); +#ifdef CONFIG_NVGPU_NON_FUSA if ((gr_intr & gr_intr_notify_pending_f()) != 0U) { intr_info->notify = gr_intr_notify_pending_f(); } @@ -61,6 +62,7 @@ u32 gm20b_gr_intr_read_pending_interrupts(struct gk20a *g, if ((gr_intr & gr_intr_semaphore_pending_f()) != 0U) { intr_info->semaphore = gr_intr_semaphore_pending_f(); } +#endif if ((gr_intr & gr_intr_illegal_notify_pending_f()) != 0U) { intr_info->illegal_notify = gr_intr_illegal_notify_pending_f();