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gpu: nvgpu: fix pmm chiplet offsets
gr_gv100_init_hwpm_pmm_register() and gr_gv100_set_pmm_register() right now assume common chiplet stride for all sys/fbp/gpc and use common API g->ops.perf.get_pmm_per_chiplet_offset() to get the stride. Chiplet strides are same for all partitions only by chance, and future chip might change that. Hence add and use below 3 separate HALs to get appropriate strides. g->ops.perf.get_pmmsys_per_chiplet_offset() g->ops.perf.get_pmmgpc_per_chiplet_offset() g->ops.perf.get_pmmfbp_per_chiplet_offset() Also store sys/fbp/gpc perfmon count in struct gk20a after first query instead of querying them again and again. Querying the counts from HW is time consuming. Bug 2510974 Jira NVGPU-5360 Change-Id: I186009221009780d561617c0cd6f535854db585f Signed-off-by: Deepak Nibade <dnibade@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2413108 Reviewed-by: automaticguardword <automaticguardword@nvidia.com> Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com> Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com> Reviewed-by: Antony Clince Alex <aalex@nvidia.com> Reviewed-by: Alex Waterman <alexw@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> GVS: Gerrit_Virtual_Submit Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
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committed by
Alex Waterman
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db20451d0d
@@ -43,7 +43,9 @@ void gm20b_perf_disable_membuf(struct gk20a *g);
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void gm20b_perf_init_inst_block(struct gk20a *g, struct nvgpu_mem *inst_block);
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void gm20b_perf_deinit_inst_block(struct gk20a *g);
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u32 gm20b_perf_get_pmm_per_chiplet_offset(void);
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u32 gm20b_perf_get_pmmsys_per_chiplet_offset(void);
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u32 gm20b_perf_get_pmmgpc_per_chiplet_offset(void);
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u32 gm20b_perf_get_pmmfbp_per_chiplet_offset(void);
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#endif /* CONFIG_NVGPU_DEBUGGER */
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#endif
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