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gpu: nvgpu: fix pmm chiplet offsets

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gr_gv100_init_hwpm_pmm_register() and gr_gv100_set_pmm_register() right
now assume common chiplet stride for all sys/fbp/gpc and use common API
g->ops.perf.get_pmm_per_chiplet_offset() to get the stride.

Chiplet strides are same for all partitions only by chance, and future
chip might change that.

Hence add and use below 3 separate HALs to get appropriate strides.
g->ops.perf.get_pmmsys_per_chiplet_offset()
g->ops.perf.get_pmmgpc_per_chiplet_offset()
g->ops.perf.get_pmmfbp_per_chiplet_offset()

Also store sys/fbp/gpc perfmon count in struct gk20a after first query
instead of querying them again and again. Querying the counts from HW
is time consuming.

Bug 2510974
Jira NVGPU-5360

Change-Id: I186009221009780d561617c0cd6f535854db585f
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2413108
Reviewed-by: automaticguardword <automaticguardword@nvidia.com>
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
Reviewed-by: Antony Clince Alex <aalex@nvidia.com>
Reviewed-by: Alex Waterman <alexw@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
GVS: Gerrit_Virtual_Submit
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
This commit is contained in:
Deepak Nibade
2020-09-11 12:29:55 +05:30
committed by Alex Waterman
parent d419005222
commit db20451d0d
22 changed files with 91 additions and 39 deletions
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12
drivers/gpu/nvgpu/hal/perf/perf_gv11b.c
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@@ -109,7 +109,17 @@ void gv11b_perf_deinit_inst_block(struct gk20a *g)
perf_pmasys_mem_block_target_f(0));
}
u32 gv11b_perf_get_pmm_per_chiplet_offset(void)
u32 gv11b_perf_get_pmmsys_per_chiplet_offset(void)
{
return (perf_pmmsys_extent_v() - perf_pmmsys_base_v() + 1U);
}
u32 gv11b_perf_get_pmmgpc_per_chiplet_offset(void)
{
return (perf_pmmgpc_extent_v() - perf_pmmgpc_base_v() + 1U);
}
u32 gv11b_perf_get_pmmfbp_per_chiplet_offset(void)
{
return (perf_pmmfbp_extent_v() - perf_pmmfbp_base_v() + 1U);
}