gpu: nvgpu: fix pmm chiplet offsets

gr_gv100_init_hwpm_pmm_register() and gr_gv100_set_pmm_register() right
now assume common chiplet stride for all sys/fbp/gpc and use common API
g->ops.perf.get_pmm_per_chiplet_offset() to get the stride.

Chiplet strides are same for all partitions only by chance, and future
chip might change that.

Hence add and use below 3 separate HALs to get appropriate strides.
g->ops.perf.get_pmmsys_per_chiplet_offset()
g->ops.perf.get_pmmgpc_per_chiplet_offset()
g->ops.perf.get_pmmfbp_per_chiplet_offset()

Also store sys/fbp/gpc perfmon count in struct gk20a after first query
instead of querying them again and again. Querying the counts from HW
is time consuming.

Bug 2510974
Jira NVGPU-5360

Change-Id: I186009221009780d561617c0cd6f535854db585f
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2413108
Reviewed-by: automaticguardword <automaticguardword@nvidia.com>
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
Reviewed-by: Antony Clince Alex <aalex@nvidia.com>
Reviewed-by: Alex Waterman <alexw@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
GVS: Gerrit_Virtual_Submit
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>

drivers/gpu/nvgpu/common/gr/hwpm_map.c

@@ -274,7 +274,7 @@ static int add_ctxsw_buffer_map_entries_gpcs(struct gk20a *g,
 			return -EINVAL;
 		}
 
-		base = (g->ops.perf.get_pmm_per_chiplet_offset() * gpc_num);
+		base = (g->ops.perf.get_pmmgpc_per_chiplet_offset() * gpc_num);
 		if (add_ctxsw_buffer_map_entries(map,
 				nvgpu_netlist_get_perf_gpc_ctxsw_regs(g),
 				count, offset, max_cnt, base, ~U32(0U)) != 0) {
@@ -303,7 +303,7 @@ static int add_ctxsw_buffer_map_entries_gpcs(struct gk20a *g,
 
 		*offset = ALIGN(*offset, 256U);
 
-		base = (g->ops.perf.get_pmm_per_chiplet_offset() * gpc_num);
+		base = (g->ops.perf.get_pmmgpc_per_chiplet_offset() * gpc_num);
 		if (add_ctxsw_buffer_map_entries(map,
 				nvgpu_netlist_get_perf_gpc_control_ctxsw_regs(g),
 				count, offset, max_cnt, base, ~U32(0U)) != 0) {
@@ -466,7 +466,7 @@ static int nvgpu_gr_hwpm_map_create(struct gk20a *g,
 	if (add_ctxsw_buffer_map_entries_subunits(map,
 		nvgpu_netlist_get_fbp_ctxsw_regs(g), &count, &offset,
 			hwpm_ctxsw_reg_count_max, 0, num_fbps, ~U32(0U),
-			g->ops.perf.get_pmm_per_chiplet_offset(),
+			g->ops.perf.get_pmmfbp_per_chiplet_offset(),
 			~U32(0U)) != 0) {
 		goto cleanup;
 	}
@@ -517,7 +517,7 @@ static int nvgpu_gr_hwpm_map_create(struct gk20a *g,
 			nvgpu_netlist_get_perf_fbp_control_ctxsw_regs(g),
 			&count, &offset, hwpm_ctxsw_reg_count_max, 0,
 			num_fbps, ~U32(0U),
-			g->ops.perf.get_pmm_per_chiplet_offset(),
+			g->ops.perf.get_pmmfbp_per_chiplet_offset(),
 			~U32(0U)) != 0) {
 		goto cleanup;
 	}

drivers/gpu/nvgpu/hal/gr/gr/gr_gm20b.h

@@ -59,7 +59,6 @@ void gr_gm20b_init_cyclestats(struct gk20a *g);
 void gr_gm20b_bpt_reg_info(struct gk20a *g, struct nvgpu_warpstate *w_state);
 int gm20b_gr_clear_sm_error_state(struct gk20a *g,
 		struct nvgpu_channel *ch, u32 sm_id);
-u32 gr_gm20b_get_pmm_per_chiplet_offset(void);
 void gm20b_gr_set_debug_mode(struct gk20a *g, bool enable);
 int gm20b_gr_set_mmu_debug_mode(struct gk20a *g,
 		struct nvgpu_channel *ch, bool enable);

drivers/gpu/nvgpu/hal/gr/gr/gr_gv100.c

@@ -84,12 +84,11 @@ void gr_gv100_split_fbpa_broadcast_addr(struct gk20a *g, u32 addr,
 }
 
 void gr_gv100_set_pmm_register(struct gk20a *g, u32 offset, u32 val,
-				u32 num_chiplets, u32 num_perfmons)
+		u32 num_chiplets, u32 chiplet_stride, u32 num_perfmons)
 {
 	u32 perfmon_index = 0;
 	u32 chiplet_index = 0;
 	u32 reg_offset = 0;
-	u32 chiplet_stride = g->ops.perf.get_pmm_per_chiplet_offset();
 
 	for (chiplet_index = 0; chiplet_index < num_chiplets; chiplet_index++) {
 		for (perfmon_index = 0; perfmon_index < num_perfmons;
@@ -157,18 +156,20 @@ void gr_gv100_get_num_hwpm_perfmon(struct gk20a *g, u32 *num_sys_perfmon,
 
 void gr_gv100_init_hwpm_pmm_register(struct gk20a *g)
 {
-	u32 num_sys_perfmon = 0;
+	if (g->num_sys_perfmon == 0U) {
-	u32 num_fbp_perfmon = 0;
+		g->ops.gr.get_num_hwpm_perfmon(g, &g->num_sys_perfmon,
-	u32 num_gpc_perfmon = 0;
+				&g->num_fbp_perfmon, &g->num_gpc_perfmon);
+	}
 
-	g->ops.gr.get_num_hwpm_perfmon(g, &num_sys_perfmon,
+	g->ops.gr.set_pmm_register(g, perf_pmmsys_engine_sel_r(0), 0xFFFFFFFFU,
-				&num_fbp_perfmon, &num_gpc_perfmon);
+		1U, g->ops.perf.get_pmmsys_per_chiplet_offset(),
-
+		g->num_sys_perfmon);
-	g->ops.gr.set_pmm_register(g, perf_pmmsys_engine_sel_r(0),
+	g->ops.gr.set_pmm_register(g, perf_pmmfbp_engine_sel_r(0), 0xFFFFFFFFU,
-		0xFFFFFFFFU, 1U, num_sys_perfmon);
+		nvgpu_fbp_get_num_fbps(g->fbp),
-	g->ops.gr.set_pmm_register(g, perf_pmmfbp_engine_sel_r(0),
+		g->ops.perf.get_pmmfbp_per_chiplet_offset(),
-		0xFFFFFFFFU, nvgpu_fbp_get_num_fbps(g->fbp), num_fbp_perfmon);
+		g->num_fbp_perfmon);
-	g->ops.gr.set_pmm_register(g, perf_pmmgpc_engine_sel_r(0),
+	g->ops.gr.set_pmm_register(g, perf_pmmgpc_engine_sel_r(0), 0xFFFFFFFFU,
-		0xFFFFFFFFU, nvgpu_gr_config_get_gpc_count(g->gr->config),
+		nvgpu_gr_config_get_gpc_count(g->gr->config),
-		num_gpc_perfmon);
+		g->ops.perf.get_pmmgpc_per_chiplet_offset(),
+		g->num_gpc_perfmon);
 }

drivers/gpu/nvgpu/hal/gr/gr/gr_gv100.h

@@ -39,7 +39,7 @@ void gr_gv100_split_fbpa_broadcast_addr(struct gk20a *g, u32 addr,
 	u32 *priv_addr_table, u32 *t);
 void gr_gv100_init_hwpm_pmm_register(struct gk20a *g);
 void gr_gv100_set_pmm_register(struct gk20a *g, u32 offset, u32 val,
-				u32 num_chiplets, u32 num_perfmons);
+		u32 num_chiplets, u32 chiplet_stride, u32 num_perfmons);
 void gr_gv100_get_num_hwpm_perfmon(struct gk20a *g, u32 *num_sys_perfmon,
 				u32 *num_fbp_perfmon, u32 *num_gpc_perfmon);
 #endif /* CONFIG_NVGPU_DEBUGGER */

drivers/gpu/nvgpu/hal/gr/gr/gr_gv11b.c

@@ -1856,7 +1856,7 @@ static u32 gr_gv11b_pri_pmmgpc_addr(struct gk20a *g, u32 gpc_num,
 	u32 domain_idx, u32 offset)
 {
 	return perf_pmmgpc_base_v() +
-		(gpc_num * g->ops.perf.get_pmm_per_chiplet_offset()) +
+		(gpc_num * g->ops.perf.get_pmmgpc_per_chiplet_offset()) +
 		(domain_idx * perf_pmmgpc_perdomain_offset_v()) +
 		offset;
 }
@@ -1871,7 +1871,7 @@ static void gr_gv11b_split_pmm_fbp_broadcast_address(struct gk20a *g,
 
 	for (fbp_num = 0; fbp_num < nvgpu_fbp_get_num_fbps(g->fbp); fbp_num++) {
 		base = perf_pmmfbp_base_v() +
-			(fbp_num * g->ops.perf.get_pmm_per_chiplet_offset());
+			(fbp_num * g->ops.perf.get_pmmfbp_per_chiplet_offset());
 
 		for (domain_idx = domain_start;
 		     domain_idx < (domain_start + num_domains);

drivers/gpu/nvgpu/hal/init/hal_gm20b.c

@@ -918,7 +918,9 @@ static const struct gops_perf gm20b_ops_perf = {
 	.get_membuf_pending_bytes = gm20b_perf_get_membuf_pending_bytes,
 	.set_membuf_handled_bytes = gm20b_perf_set_membuf_handled_bytes,
 	.get_membuf_overflow_status = gm20b_perf_get_membuf_overflow_status,
-	.get_pmm_per_chiplet_offset = gm20b_perf_get_pmm_per_chiplet_offset,
+	.get_pmmsys_per_chiplet_offset = gm20b_perf_get_pmmsys_per_chiplet_offset,
+	.get_pmmgpc_per_chiplet_offset = gm20b_perf_get_pmmgpc_per_chiplet_offset,
+	.get_pmmfbp_per_chiplet_offset = gm20b_perf_get_pmmfbp_per_chiplet_offset,
 };
 #endif
 

drivers/gpu/nvgpu/hal/init/hal_gp10b.c

@@ -1003,7 +1003,9 @@ static const struct gops_perf gp10b_ops_perf = {
 	.get_membuf_pending_bytes = gm20b_perf_get_membuf_pending_bytes,
 	.set_membuf_handled_bytes = gm20b_perf_set_membuf_handled_bytes,
 	.get_membuf_overflow_status = gm20b_perf_get_membuf_overflow_status,
-	.get_pmm_per_chiplet_offset = gm20b_perf_get_pmm_per_chiplet_offset,
+	.get_pmmsys_per_chiplet_offset = gm20b_perf_get_pmmsys_per_chiplet_offset,
+	.get_pmmgpc_per_chiplet_offset = gm20b_perf_get_pmmgpc_per_chiplet_offset,
+	.get_pmmfbp_per_chiplet_offset = gm20b_perf_get_pmmfbp_per_chiplet_offset,
 };
 #endif
 

drivers/gpu/nvgpu/hal/init/hal_gv11b.c

@@ -1220,7 +1220,9 @@ static const struct gops_perf gv11b_ops_perf = {
 	.get_membuf_pending_bytes = gv11b_perf_get_membuf_pending_bytes,
 	.set_membuf_handled_bytes = gv11b_perf_set_membuf_handled_bytes,
 	.get_membuf_overflow_status = gv11b_perf_get_membuf_overflow_status,
-	.get_pmm_per_chiplet_offset = gv11b_perf_get_pmm_per_chiplet_offset,
+	.get_pmmsys_per_chiplet_offset = gv11b_perf_get_pmmsys_per_chiplet_offset,
+	.get_pmmgpc_per_chiplet_offset = gv11b_perf_get_pmmgpc_per_chiplet_offset,
+	.get_pmmfbp_per_chiplet_offset = gv11b_perf_get_pmmfbp_per_chiplet_offset,
 };
 #endif
 

drivers/gpu/nvgpu/hal/init/hal_tu104.c

@@ -1288,7 +1288,9 @@ static const struct gops_perf tu104_ops_perf = {
 	.get_membuf_pending_bytes = gv11b_perf_get_membuf_pending_bytes,
 	.set_membuf_handled_bytes = gv11b_perf_set_membuf_handled_bytes,
 	.get_membuf_overflow_status = gv11b_perf_get_membuf_overflow_status,
-	.get_pmm_per_chiplet_offset = gv11b_perf_get_pmm_per_chiplet_offset,
+	.get_pmmsys_per_chiplet_offset = gv11b_perf_get_pmmsys_per_chiplet_offset,
+	.get_pmmgpc_per_chiplet_offset = gv11b_perf_get_pmmgpc_per_chiplet_offset,
+	.get_pmmfbp_per_chiplet_offset = gv11b_perf_get_pmmfbp_per_chiplet_offset,
 };
 #endif
 

drivers/gpu/nvgpu/hal/perf/perf_gm20b.c

@@ -110,7 +110,17 @@ void gm20b_perf_deinit_inst_block(struct gk20a *g)
 			perf_pmasys_mem_block_target_f(0));
 }
 
-u32 gm20b_perf_get_pmm_per_chiplet_offset(void)
+u32 gm20b_perf_get_pmmsys_per_chiplet_offset(void)
 {
 	return (perf_pmmsys_extent_v() - perf_pmmsys_base_v() + 1U);
 }
+
+u32 gm20b_perf_get_pmmgpc_per_chiplet_offset(void)
+{
+	return (perf_pmmgpc_extent_v() - perf_pmmgpc_base_v() + 1U);
+}
+
+u32 gm20b_perf_get_pmmfbp_per_chiplet_offset(void)
+{
+	return (perf_pmmfbp_extent_v() - perf_pmmfbp_base_v() + 1U);
+}

drivers/gpu/nvgpu/hal/perf/perf_gm20b.h

@@ -43,7 +43,9 @@ void gm20b_perf_disable_membuf(struct gk20a *g);
 void gm20b_perf_init_inst_block(struct gk20a *g, struct nvgpu_mem *inst_block);
 void gm20b_perf_deinit_inst_block(struct gk20a *g);
 
-u32 gm20b_perf_get_pmm_per_chiplet_offset(void);
+u32 gm20b_perf_get_pmmsys_per_chiplet_offset(void);
+u32 gm20b_perf_get_pmmgpc_per_chiplet_offset(void);
+u32 gm20b_perf_get_pmmfbp_per_chiplet_offset(void);
 
 #endif /* CONFIG_NVGPU_DEBUGGER */
 #endif

drivers/gpu/nvgpu/hal/perf/perf_gv11b.c

@@ -109,7 +109,17 @@ void gv11b_perf_deinit_inst_block(struct gk20a *g)
 			perf_pmasys_mem_block_target_f(0));
 }
 
-u32 gv11b_perf_get_pmm_per_chiplet_offset(void)
+u32 gv11b_perf_get_pmmsys_per_chiplet_offset(void)
 {
 	return (perf_pmmsys_extent_v() - perf_pmmsys_base_v() + 1U);
 }
+
+u32 gv11b_perf_get_pmmgpc_per_chiplet_offset(void)
+{
+	return (perf_pmmgpc_extent_v() - perf_pmmgpc_base_v() + 1U);
+}
+
+u32 gv11b_perf_get_pmmfbp_per_chiplet_offset(void)
+{
+	return (perf_pmmfbp_extent_v() - perf_pmmfbp_base_v() + 1U);
+}

drivers/gpu/nvgpu/hal/perf/perf_gv11b.h

@@ -43,7 +43,9 @@ void gv11b_perf_disable_membuf(struct gk20a *g);
 void gv11b_perf_init_inst_block(struct gk20a *g, struct nvgpu_mem *inst_block);
 void gv11b_perf_deinit_inst_block(struct gk20a *g);
 
-u32 gv11b_perf_get_pmm_per_chiplet_offset(void);
+u32 gv11b_perf_get_pmmsys_per_chiplet_offset(void);
+u32 gv11b_perf_get_pmmgpc_per_chiplet_offset(void);
+u32 gv11b_perf_get_pmmfbp_per_chiplet_offset(void);
 
 #endif /* CONFIG_NVGPU_DEBUGGER */
 #endif

drivers/gpu/nvgpu/hal/vgpu/init/vgpu_hal_gp10b.c

@@ -760,7 +760,9 @@ static const struct gops_debugger vgpu_gp10b_ops_debugger = {
 
 #ifdef CONFIG_NVGPU_DEBUGGER
 static const struct gops_perf vgpu_gp10b_ops_perf = {
-	.get_pmm_per_chiplet_offset = gm20b_perf_get_pmm_per_chiplet_offset,
+	.get_pmmsys_per_chiplet_offset = gm20b_perf_get_pmmsys_per_chiplet_offset,
+	.get_pmmgpc_per_chiplet_offset = gm20b_perf_get_pmmgpc_per_chiplet_offset,
+	.get_pmmfbp_per_chiplet_offset = gm20b_perf_get_pmmfbp_per_chiplet_offset,
 };
 #endif
 

drivers/gpu/nvgpu/hal/vgpu/init/vgpu_hal_gv11b.c

@@ -872,7 +872,9 @@ static const struct gops_debugger vgpu_gv11b_ops_debugger = {
 
 #ifdef CONFIG_NVGPU_DEBUGGER
 static const struct gops_perf vgpu_gv11b_ops_perf = {
-	.get_pmm_per_chiplet_offset = gv11b_perf_get_pmm_per_chiplet_offset,
+	.get_pmmsys_per_chiplet_offset = gv11b_perf_get_pmmsys_per_chiplet_offset,
+	.get_pmmgpc_per_chiplet_offset = gv11b_perf_get_pmmgpc_per_chiplet_offset,
+	.get_pmmfbp_per_chiplet_offset = gv11b_perf_get_pmmfbp_per_chiplet_offset,
 };
 #endif
 

drivers/gpu/nvgpu/include/nvgpu/gk20a.h

@@ -442,6 +442,10 @@ struct gk20a {
 	struct nvgpu_list_node profiler_objects;
 	struct nvgpu_pm_resource_reservations *pm_reservations;
 	nvgpu_atomic_t hwpm_refcount;
+
+	u32 num_sys_perfmon;
+	u32 num_gpc_perfmon;
+	u32 num_fbp_perfmon;
 #endif
 
 #ifdef CONFIG_NVGPU_FECS_TRACE

drivers/gpu/nvgpu/include/nvgpu/gops/debugger.h

@@ -54,7 +54,9 @@ struct gops_perf {
 	void (*set_membuf_handled_bytes)(struct gk20a *g,
 		u32 entries, u32 entry_size);
 	bool (*get_membuf_overflow_status)(struct gk20a *g);
-	u32 (*get_pmm_per_chiplet_offset)(void);
+	u32 (*get_pmmsys_per_chiplet_offset)(void);
+	u32 (*get_pmmgpc_per_chiplet_offset)(void);
+	u32 (*get_pmmfbp_per_chiplet_offset)(void);
 };
 struct gops_perfbuf {
 	int (*perfbuf_enable)(struct gk20a *g, u64 offset, u32 size);

drivers/gpu/nvgpu/include/nvgpu/gops/gr.h

@@ -1085,7 +1085,7 @@ struct gops_gr {
 				     u32 *num_fbp_perfmon,
 				     u32 *num_gpc_perfmon);
 	void (*set_pmm_register)(struct gk20a *g, u32 offset, u32 val,
-				 u32 num_chiplets, u32 num_perfmons);
+			 u32 num_chiplets, u32 chiplet_stride, u32 num_perfmons);
 	int (*dump_gr_regs)(struct gk20a *g,
 			    struct nvgpu_debug_context *o);
 	int (*update_pc_sampling)(struct nvgpu_channel *ch,

drivers/gpu/nvgpu/include/nvgpu/hw/gm20b/hw_perf_gm20b.h

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2015-2019, NVIDIA CORPORATION.  All rights reserved.
+ * Copyright (c) 2015-2020, NVIDIA CORPORATION.  All rights reserved.
  *
  * Permission is hereby granted, free of charge, to any person obtaining a
  * copy of this software and associated documentation files (the "Software"),
@@ -59,8 +59,12 @@
 #include <nvgpu/types.h>
 #include <nvgpu/static_analysis.h>
 
+#define perf_pmmgpc_base_v()                                       (0x00180000U)
+#define perf_pmmgpc_extent_v()                                     (0x00180fffU)
 #define perf_pmmsys_base_v()                                       (0x001b0000U)
 #define perf_pmmsys_extent_v()                                     (0x001b0fffU)
+#define perf_pmmfbp_base_v()                                       (0x001a0000U)
+#define perf_pmmfbp_extent_v()                                     (0x001a0fffU)
 #define perf_pmasys_control_r()                                    (0x001b4000U)
 #define perf_pmasys_control_membuf_status_v(r)              (((r) >> 4U) & 0x1U)
 #define perf_pmasys_control_membuf_status_overflowed_v()           (0x00000001U)

drivers/gpu/nvgpu/include/nvgpu/hw/gp10b/hw_perf_gp10b.h

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2015-2019, NVIDIA CORPORATION.  All rights reserved.
+ * Copyright (c) 2015-2020, NVIDIA CORPORATION.  All rights reserved.
  *
  * Permission is hereby granted, free of charge, to any person obtaining a
  * copy of this software and associated documentation files (the "Software"),
@@ -59,8 +59,12 @@
 #include <nvgpu/types.h>
 #include <nvgpu/static_analysis.h>
 
+#define perf_pmmgpc_base_v()                                       (0x00180000U)
+#define perf_pmmgpc_extent_v()                                     (0x00180fffU)
 #define perf_pmmsys_base_v()                                       (0x001b0000U)
 #define perf_pmmsys_extent_v()                                     (0x001b0fffU)
+#define perf_pmmfbp_base_v()                                       (0x001a0000U)
+#define perf_pmmfbp_extent_v()                                     (0x001a0fffU)
 #define perf_pmasys_control_r()                                    (0x001b4000U)
 #define perf_pmasys_control_membuf_status_v(r)              (((r) >> 4U) & 0x1U)
 #define perf_pmasys_control_membuf_status_overflowed_v()           (0x00000001U)

drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_perf_gv11b.h

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2016-2019, NVIDIA CORPORATION.  All rights reserved.
+ * Copyright (c) 2016-2020, NVIDIA CORPORATION.  All rights reserved.
  *
  * Permission is hereby granted, free of charge, to any person obtaining a
  * copy of this software and associated documentation files (the "Software"),
@@ -66,6 +66,7 @@
 #define perf_pmmsys_base_v()                                       (0x00240000U)
 #define perf_pmmsys_extent_v()                                     (0x00243fffU)
 #define perf_pmmfbp_base_v()                                       (0x00200000U)
+#define perf_pmmfbp_extent_v()                                     (0x00203fffU)
 #define perf_pmasys_control_r()                                    (0x0024a000U)
 #define perf_pmasys_control_membuf_status_v(r)              (((r) >> 4U) & 0x1U)
 #define perf_pmasys_control_membuf_status_overflowed_v()           (0x00000001U)

drivers/gpu/nvgpu/include/nvgpu/hw/tu104/hw_perf_tu104.h

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2018-2019, NVIDIA CORPORATION.  All rights reserved.
+ * Copyright (c) 2018-2020, NVIDIA CORPORATION.  All rights reserved.
  *
  * Permission is hereby granted, free of charge, to any person obtaining a
  * copy of this software and associated documentation files (the "Software"),
@@ -66,6 +66,7 @@
 #define perf_pmmsys_base_v()                                       (0x00240000U)
 #define perf_pmmsys_extent_v()                                     (0x00243fffU)
 #define perf_pmmfbp_base_v()                                       (0x00200000U)
+#define perf_pmmfbp_extent_v()                                     (0x00203fffU)
 #define perf_pmasys_control_r()                                    (0x0024a000U)
 #define perf_pmasys_control_membuf_status_v(r)              (((r) >> 4U) & 0x1U)
 #define perf_pmasys_control_membuf_status_overflowed_v()           (0x00000001U)