diff --git a/drivers/gpu/nvgpu/hal/init/hal_ga100.c b/drivers/gpu/nvgpu/hal/init/hal_ga100.c
index b4404bbea..34daf5752 100644
--- a/drivers/gpu/nvgpu/hal/init/hal_ga100.c
+++ b/drivers/gpu/nvgpu/hal/init/hal_ga100.c
@@ -376,6 +376,12 @@ static const struct gops_ltc_intr ga100_ops_ltc_intr = {
 	.en_illegal_compstat = gv11b_ltc_intr_en_illegal_compstat,
 	.handle_illegal_compstat = ga10b_ltc_intr_handle_illegal_compstat,
 #endif
+	.read_intr1 = ga10b_ltc_intr_read_intr1,
+	.read_intr2 = ga10b_ltc_intr_read_intr2,
+	.read_intr3 = ga10b_ltc_intr_read_intr3,
+	.write_intr1 = ga10b_ltc_intr_write_intr1,
+	.write_intr2 = ga10b_ltc_intr_write_intr2,
+	.write_intr3 = ga10b_ltc_intr_write_intr3,
 };
 
 static const struct gops_ltc ga100_ops_ltc = {
diff --git a/drivers/gpu/nvgpu/hal/init/hal_ga10b.c b/drivers/gpu/nvgpu/hal/init/hal_ga10b.c
index af20ec875..25ccd84f8 100644
--- a/drivers/gpu/nvgpu/hal/init/hal_ga10b.c
+++ b/drivers/gpu/nvgpu/hal/init/hal_ga10b.c
@@ -350,6 +350,12 @@ static const struct gops_ltc_intr ga10b_ops_ltc_intr = {
 	.en_illegal_compstat = gv11b_ltc_intr_en_illegal_compstat,
 	.handle_illegal_compstat = ga10b_ltc_intr_handle_illegal_compstat,
 #endif
+	.read_intr1 = ga10b_ltc_intr_read_intr1,
+	.read_intr2 = ga10b_ltc_intr_read_intr2,
+	.read_intr3 = ga10b_ltc_intr_read_intr3,
+	.write_intr1 = ga10b_ltc_intr_write_intr1,
+	.write_intr2 = ga10b_ltc_intr_write_intr2,
+	.write_intr3 = ga10b_ltc_intr_write_intr3,
 };
 
 static const struct gops_ltc ga10b_ops_ltc = {
diff --git a/drivers/gpu/nvgpu/hal/ltc/intr/ltc_intr_ga10b.h b/drivers/gpu/nvgpu/hal/ltc/intr/ltc_intr_ga10b.h
index 2990c9117..caefaba8e 100644
--- a/drivers/gpu/nvgpu/hal/ltc/intr/ltc_intr_ga10b.h
+++ b/drivers/gpu/nvgpu/hal/ltc/intr/ltc_intr_ga10b.h
@@ -40,5 +40,11 @@ void ga10b_ltc_intr_handle_lts_intr3(struct gk20a *g, u32 ltc, u32 slice);
 void ga10b_ltc_intr_handle_lts_intr3_extra(struct gk20a *g, u32 ltc, u32 slice, u32 *reg_value);
 void ga10b_ltc_intr_handle_illegal_compstat(struct gk20a *g, u32 ltc, u32 slice,
 				u32 ltc_intr, u32 *reg_value);
+u32 ga10b_ltc_intr_read_intr1(struct gk20a *g);
+u32 ga10b_ltc_intr_read_intr2(struct gk20a *g);
+u32 ga10b_ltc_intr_read_intr3(struct gk20a *g);
+void ga10b_ltc_intr_write_intr1(struct gk20a *g, u32 reg_val);
+void ga10b_ltc_intr_write_intr2(struct gk20a *g, u32 reg_val);
+void ga10b_ltc_intr_write_intr3(struct gk20a *g, u32 reg_val);
 
 #endif /* NVGPU_LTC_INTR_GA10B_H */
diff --git a/drivers/gpu/nvgpu/hal/ltc/intr/ltc_intr_ga10b_fusa.c b/drivers/gpu/nvgpu/hal/ltc/intr/ltc_intr_ga10b_fusa.c
index 3ae3a776d..1ab6a38ad 100644
--- a/drivers/gpu/nvgpu/hal/ltc/intr/ltc_intr_ga10b_fusa.c
+++ b/drivers/gpu/nvgpu/hal/ltc/intr/ltc_intr_ga10b_fusa.c
@@ -32,12 +32,42 @@
 
 #include <nvgpu/hw/ga10b/hw_ltc_ga10b.h>
 
+u32 ga10b_ltc_intr_read_intr1(struct gk20a *g)
+{
+	return nvgpu_readl(g, ltc_ltcs_ltss_intr_r());
+}
+
+u32 ga10b_ltc_intr_read_intr2(struct gk20a *g)
+{
+	return nvgpu_readl(g, ltc_ltcs_ltss_intr2_r());
+}
+
+u32 ga10b_ltc_intr_read_intr3(struct gk20a *g)
+{
+	return nvgpu_readl(g, ltc_ltcs_ltss_intr3_r());
+}
+
+void ga10b_ltc_intr_write_intr1(struct gk20a *g, u32 reg_val)
+{
+	nvgpu_writel(g, ltc_ltcs_ltss_intr_r(), reg_val);
+}
+
+void ga10b_ltc_intr_write_intr2(struct gk20a *g, u32 reg_val)
+{
+	nvgpu_writel(g, ltc_ltcs_ltss_intr2_r(), reg_val);
+}
+
+void ga10b_ltc_intr_write_intr3(struct gk20a *g, u32 reg_val)
+{
+	nvgpu_writel(g, ltc_ltcs_ltss_intr3_r(), reg_val);
+}
+
 static void ga10b_ltc_intr1_configure(struct gk20a *g)
 {
 	u32 reg;
 
 	/* Enable ltc interrupts indicating illegal activity */
-	reg = nvgpu_readl(g, ltc_ltcs_ltss_intr_r());
+	reg = g->ops.ltc.intr.read_intr1(g);
 
 	/*
 	 * IDLE_ERROR_CBC - flag if cbc gets a request while slcg clock is
@@ -92,10 +122,10 @@ static void ga10b_ltc_intr1_configure(struct gk20a *g)
 	reg = set_field(reg, ltc_ltcs_ltss_intr_en_illegal_compstat_access_m(),
 		ltc_ltcs_ltss_intr_en_illegal_compstat_access_enabled_f());
 
-	nvgpu_writel(g, ltc_ltcs_ltss_intr_r(), reg);
+	g->ops.ltc.intr.write_intr1(g, reg);
 
 	/* Read back register for write synchronization */
-	reg = nvgpu_readl(g, ltc_ltcs_ltss_intr_r());
+	reg = g->ops.ltc.intr.read_intr1(g);
 
 #ifdef CONFIG_NVGPU_NON_FUSA
 	/* illegal_compstat interrupts can be also controlled through
@@ -114,7 +144,7 @@ static void ga10b_ltc_intr2_configure(struct gk20a *g)
 {
 	u32 reg;
 
-	reg = nvgpu_readl(g, ltc_ltcs_ltss_intr2_r());
+	reg = g->ops.ltc.intr.read_intr2(g);
 
 	/*
 	 * TRDONE_INVALID_TDTAG - The tdtag for a transdone does not match any
@@ -244,10 +274,10 @@ static void ga10b_ltc_intr2_configure(struct gk20a *g)
 		ltc_ltcs_ltss_intr2_en_checkedin_unexpected_trdone_m(),
 		ltc_ltcs_ltss_intr2_en_checkedin_unexpected_trdone_enabled_f());
 
-	nvgpu_writel(g, ltc_ltcs_ltss_intr2_r(), reg);
+	g->ops.ltc.intr.write_intr2(g, reg);
 
 	/* Read back register for write synchronization */
-	reg = nvgpu_readl(g, ltc_ltcs_ltss_intr2_r());
+	reg = g->ops.ltc.intr.read_intr2(g);
 }
 
 void ga10b_ltc_intr3_configure_extra(struct gk20a *g, u32 *reg)
@@ -294,7 +324,7 @@ static void ga10b_ltc_intr3_configure(struct gk20a *g)
 {
 	u32 reg;
 
-	reg = nvgpu_readl(g, ltc_ltcs_ltss_intr3_r());
+	reg = g->ops.ltc.intr.read_intr3(g);
 
 	/*
 	 * CHECKEDOUT_RWC_UPG_UNEXPECTED_NVPORT - RWC/Upgrade to the same 256B
@@ -379,10 +409,10 @@ static void ga10b_ltc_intr3_configure(struct gk20a *g)
 		g->ops.ltc.intr.ltc_intr3_configure_extra(g, &reg);
 	}
 
-	nvgpu_writel(g, ltc_ltcs_ltss_intr3_r(), reg);
+	g->ops.ltc.intr.write_intr3(g, reg);
 
 	/* Read back register for write synchronization */
-	reg = nvgpu_readl(g, ltc_ltcs_ltss_intr3_r());
+	reg = g->ops.ltc.intr.read_intr3(g);
 }
 
 void ga10b_ltc_intr_configure(struct gk20a *g)
diff --git a/drivers/gpu/nvgpu/include/nvgpu/gops/ltc.h b/drivers/gpu/nvgpu/include/nvgpu/gops/ltc.h
index db41d5fd9..9ce784567 100644
--- a/drivers/gpu/nvgpu/include/nvgpu/gops/ltc.h
+++ b/drivers/gpu/nvgpu/include/nvgpu/gops/ltc.h
@@ -200,6 +200,12 @@ struct gops_ltc_intr {
 
 	/** @cond DOXYGEN_SHOULD_SKIP_THIS */
 	void (*configure)(struct gk20a *g);
+	u32 (*read_intr1)(struct gk20a *g);
+	u32 (*read_intr2)(struct gk20a *g);
+	u32 (*read_intr3)(struct gk20a *g);
+	void (*write_intr1)(struct gk20a *g, u32 reg_val);
+	void (*write_intr2)(struct gk20a *g, u32 reg_val);
+	void (*write_intr3)(struct gk20a *g, u32 reg_val);
 #ifdef CONFIG_NVGPU_NON_FUSA
 	void (*en_illegal_compstat)(struct gk20a *g, bool enable);
 	void (*handle_illegal_compstat)(struct gk20a *g, u32 ltc, u32 slice,