diff --git a/drivers/gpu/nvgpu/hal/bus/bus_gk20a_fusa.c b/drivers/gpu/nvgpu/hal/bus/bus_gk20a_fusa.c
index e641e88b5..840f6b509 100644
--- a/drivers/gpu/nvgpu/hal/bus/bus_gk20a_fusa.c
+++ b/drivers/gpu/nvgpu/hal/bus/bus_gk20a_fusa.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2017-2019, NVIDIA CORPORATION.  All rights reserved.
+ * Copyright (c) 2017-2020, NVIDIA CORPORATION.  All rights reserved.
  *
  * Permission is hereby granted, free of charge, to any person obtaining a
  * copy of this software and associated documentation files (the "Software"),
@@ -36,17 +36,21 @@
 
 int gk20a_bus_init_hw(struct gk20a *g)
 {
-	u32 intr_en_mask = 0;
+	u32 intr_en_mask = 0U;
 
+	nvgpu_mc_intr_nonstall_unit_config(g, MC_INTR_UNIT_BUS, MC_INTR_ENABLE);
+
+	/*
+	 * Note: bus_intr_en_0 is for routing intr to stall tree (mc_intr_0)
+	 * bus_intr_en_1 is for routing bus intr to nostall tree (mc_intr_1)
+	 */
 	if (nvgpu_platform_is_silicon(g) || nvgpu_platform_is_fpga(g)) {
-		intr_en_mask = bus_intr_en_0_pri_squash_m() |
-				bus_intr_en_0_pri_fecserr_m() |
-				bus_intr_en_0_pri_timeout_m();
+		intr_en_mask = bus_intr_en_1_pri_squash_m() |
+				bus_intr_en_1_pri_fecserr_m() |
+				bus_intr_en_1_pri_timeout_m();
 	}
 
-	nvgpu_mc_intr_stall_unit_config(g, MC_INTR_UNIT_BUS, MC_INTR_ENABLE);
-
-	nvgpu_writel(g, bus_intr_en_0_r(), intr_en_mask);
+	nvgpu_writel(g, bus_intr_en_1_r(), intr_en_mask);
 
 	if (g->ops.bus.configure_debug_bus != NULL) {
 		g->ops.bus.configure_debug_bus(g);
diff --git a/drivers/gpu/nvgpu/hal/bus/bus_tu104.c b/drivers/gpu/nvgpu/hal/bus/bus_tu104.c
index 67c3fa592..edf30985a 100644
--- a/drivers/gpu/nvgpu/hal/bus/bus_tu104.c
+++ b/drivers/gpu/nvgpu/hal/bus/bus_tu104.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2018-2019, NVIDIA CORPORATION.  All rights reserved.
+ * Copyright (c) 2018-2020, NVIDIA CORPORATION.  All rights reserved.
  *
  * Permission is hereby granted, free of charge, to any person obtaining a
  * copy of this software and associated documentation files (the "Software"),
@@ -21,6 +21,8 @@
  */
 
 #include <nvgpu/timers.h>
+#include <nvgpu/soc.h>
+#include <nvgpu/io.h>
 #include <nvgpu/mm.h>
 #include <nvgpu/gk20a.h>
 
@@ -31,6 +33,31 @@
 #include <nvgpu/hw/tu104/hw_bus_tu104.h>
 #include <nvgpu/hw/tu104/hw_func_tu104.h>
 
+int tu104_bus_init_hw(struct gk20a *g)
+{
+	u32 intr_en_mask = 0U;
+
+	nvgpu_mc_intr_stall_unit_config(g, MC_INTR_UNIT_BUS, MC_INTR_ENABLE);
+
+	/*
+	 * Note: bus_intr_en_0 is for routing intr to stall tree (mc_intr_0)
+	 * bus_intr_en_1 is for routing bus intr to nostall tree (mc_intr_1)
+	 */
+	if (nvgpu_platform_is_silicon(g) || nvgpu_platform_is_fpga(g)) {
+		intr_en_mask = bus_intr_en_0_pri_squash_m() |
+				bus_intr_en_0_pri_fecserr_m() |
+				bus_intr_en_0_pri_timeout_m();
+	}
+
+	nvgpu_writel(g, bus_intr_en_0_r(), intr_en_mask);
+
+	if (g->ops.bus.configure_debug_bus != NULL) {
+		g->ops.bus.configure_debug_bus(g);
+	}
+
+	return 0;
+}
+
 int bus_tu104_bar2_bind(struct gk20a *g, struct nvgpu_mem *bar2_inst)
 {
 	struct nvgpu_timeout timeout;
diff --git a/drivers/gpu/nvgpu/hal/bus/bus_tu104.h b/drivers/gpu/nvgpu/hal/bus/bus_tu104.h
index 1fc7584e4..4f5c942d5 100644
--- a/drivers/gpu/nvgpu/hal/bus/bus_tu104.h
+++ b/drivers/gpu/nvgpu/hal/bus/bus_tu104.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2018, NVIDIA CORPORATION.  All rights reserved.
+ * Copyright (c) 2018-2020, NVIDIA CORPORATION.  All rights reserved.
  *
  * Permission is hereby granted, free of charge, to any person obtaining a
  * copy of this software and associated documentation files (the "Software"),
@@ -26,6 +26,7 @@
 struct gk20a;
 struct nvgpu_mem;
 
+int tu104_bus_init_hw(struct gk20a *g);
 int bus_tu104_bar2_bind(struct gk20a *g, struct nvgpu_mem *bar2_inst);
 
 #endif /* NVGPU_BUS_TU104_H */
diff --git a/drivers/gpu/nvgpu/hal/init/hal_tu104.c b/drivers/gpu/nvgpu/hal/init/hal_tu104.c
index 711160559..304a3051e 100644
--- a/drivers/gpu/nvgpu/hal/init/hal_tu104.c
+++ b/drivers/gpu/nvgpu/hal/init/hal_tu104.c
@@ -1368,7 +1368,7 @@ static const struct gpu_ops tu104_ops = {
 #endif
 		.intr_stall_unit_config = intr_tu104_stall_unit_config,
 		.intr_nonstall_unit_config = intr_tu104_nonstall_unit_config,
-		.isr_stall = mc_gp10b_isr_stall,
+		.isr_stall = mc_tu104_isr_stall,
 		.intr_stall = intr_tu104_stall,
 		.intr_stall_pause = intr_tu104_stall_pause,
 		.intr_stall_resume = intr_tu104_stall_resume,
@@ -1427,7 +1427,7 @@ static const struct gpu_ops tu104_ops = {
 	},
 #endif
 	.bus = {
-		.init_hw = gk20a_bus_init_hw,
+		.init_hw = tu104_bus_init_hw,
 		.isr = gk20a_bus_isr,
 		.bar1_bind = NULL,
 		.bar2_bind = bus_tu104_bar2_bind,
diff --git a/drivers/gpu/nvgpu/hal/mc/mc_gm20b.c b/drivers/gpu/nvgpu/hal/mc/mc_gm20b.c
index aff012922..27022cac3 100644
--- a/drivers/gpu/nvgpu/hal/mc/mc_gm20b.c
+++ b/drivers/gpu/nvgpu/hal/mc/mc_gm20b.c
@@ -85,9 +85,6 @@ void gm20b_mc_isr_stall(struct gk20a *g)
 	if ((mc_intr_0 & mc_intr_ltc_pending_f()) != 0U) {
 		g->ops.mc.ltc_isr(g);
 	}
-	if ((mc_intr_0 & mc_intr_pbus_pending_f()) != 0U) {
-		g->ops.bus.isr(g);
-	}
 }
 
 void gm20b_mc_intr_mask(struct gk20a *g)
diff --git a/drivers/gpu/nvgpu/hal/mc/mc_gm20b_fusa.c b/drivers/gpu/nvgpu/hal/mc/mc_gm20b_fusa.c
index 413a73792..1ae292d91 100644
--- a/drivers/gpu/nvgpu/hal/mc/mc_gm20b_fusa.c
+++ b/drivers/gpu/nvgpu/hal/mc/mc_gm20b_fusa.c
@@ -65,6 +65,10 @@ u32 gm20b_mc_isr_nonstall(struct gk20a *g)
 
 	mc_intr_1 = g->ops.mc.intr_nonstall(g);
 
+	if ((mc_intr_1 & mc_intr_pbus_pending_f()) != 0U) {
+		g->ops.bus.isr(g);
+	}
+
 	if (g->ops.mc.is_intr1_pending(g, NVGPU_UNIT_FIFO, mc_intr_1)) {
 		ops |= g->ops.fifo.intr_1_isr(g);
 	}
@@ -172,4 +176,4 @@ bool gm20b_mc_is_enabled(struct gk20a *g, enum nvgpu_unit unit)
 
 	return (nvgpu_readl(g, mc_enable_r()) & mask) != 0U;
 }
-#endif
\ No newline at end of file
+#endif
diff --git a/drivers/gpu/nvgpu/hal/mc/mc_gp10b.h b/drivers/gpu/nvgpu/hal/mc/mc_gp10b.h
index 68081a91b..d9258c458 100644
--- a/drivers/gpu/nvgpu/hal/mc/mc_gp10b.h
+++ b/drivers/gpu/nvgpu/hal/mc/mc_gp10b.h
@@ -31,10 +31,15 @@
 
 struct gk20a;
 enum nvgpu_unit;
+enum nvgpu_fifo_engine;
 
 void mc_gp10b_intr_mask(struct gk20a *g);
 void mc_gp10b_intr_stall_unit_config(struct gk20a *g, u32 unit, bool enable);
 void mc_gp10b_intr_nonstall_unit_config(struct gk20a *g, u32 unit, bool enable);
+void mc_gp10b_isr_stall_secondary_1(struct gk20a *g, u32 mc_intr_0);
+void mc_gp10b_isr_stall_secondary_0(struct gk20a *g, u32 mc_intr_0);
+void mc_gp10b_isr_stall_engine(struct gk20a *g,
+			enum nvgpu_fifo_engine engine_enum, u32 engine_id);
 void mc_gp10b_isr_stall(struct gk20a *g);
 bool mc_gp10b_is_intr1_pending(struct gk20a *g,
 				      enum nvgpu_unit unit, u32 mc_intr_1);
diff --git a/drivers/gpu/nvgpu/hal/mc/mc_gp10b_fusa.c b/drivers/gpu/nvgpu/hal/mc/mc_gp10b_fusa.c
index 9fc5fdcd0..ebd983129 100644
--- a/drivers/gpu/nvgpu/hal/mc/mc_gp10b_fusa.c
+++ b/drivers/gpu/nvgpu/hal/mc/mc_gp10b_fusa.c
@@ -82,15 +82,12 @@ static u32 mc_gp10b_intr_pending_f(struct gk20a *g, u32 unit)
 
 static void mc_gp10b_isr_stall_primary(struct gk20a *g, u32 mc_intr_0)
 {
-	if ((mc_intr_0 & mc_intr_pbus_pending_f()) != 0U) {
-		g->ops.bus.isr(g);
-	}
 	if ((mc_intr_0 & mc_intr_priv_ring_pending_f()) != 0U) {
 		g->ops.priv_ring.isr(g);
 	}
 }
 
-static void mc_gp10b_isr_stall_secondary_1(struct gk20a *g, u32 mc_intr_0)
+void mc_gp10b_isr_stall_secondary_1(struct gk20a *g, u32 mc_intr_0)
 {
 	if ((mc_intr_0 & mc_intr_ltc_pending_f()) != 0U) {
 		g->ops.mc.ltc_isr(g);
@@ -107,7 +104,7 @@ static void mc_gp10b_isr_stall_secondary_1(struct gk20a *g, u32 mc_intr_0)
 #endif
 }
 
-static void mc_gp10b_isr_stall_secondary_0(struct gk20a *g, u32 mc_intr_0)
+void mc_gp10b_isr_stall_secondary_0(struct gk20a *g, u32 mc_intr_0)
 {
 	if ((g->ops.mc.is_intr_hub_pending != NULL) &&
 			g->ops.mc.is_intr_hub_pending(g, mc_intr_0)) {
@@ -121,7 +118,7 @@ static void mc_gp10b_isr_stall_secondary_0(struct gk20a *g, u32 mc_intr_0)
 	}
 }
 
-static void mc_gp10b_isr_stall_engine(struct gk20a *g,
+void mc_gp10b_isr_stall_engine(struct gk20a *g,
 			enum nvgpu_fifo_engine engine_enum, u32 engine_id)
 {
 	/* GR Engine */
diff --git a/drivers/gpu/nvgpu/hal/mc/mc_gv11b_fusa.c b/drivers/gpu/nvgpu/hal/mc/mc_gv11b_fusa.c
index 401e99028..14d364878 100644
--- a/drivers/gpu/nvgpu/hal/mc/mc_gv11b_fusa.c
+++ b/drivers/gpu/nvgpu/hal/mc/mc_gv11b_fusa.c
@@ -49,7 +49,6 @@ bool gv11b_mc_is_stall_and_eng_intr_pending(struct gk20a *g, u32 engine_id,
 	stall_intr = mc_intr_pfifo_pending_f() |
 			mc_intr_hub_pending_f() |
 			mc_intr_priv_ring_pending_f() |
-			mc_intr_pbus_pending_f() |
 			mc_intr_ltc_pending_f();
 
 	nvgpu_log(g, gpu_dbg_info | gpu_dbg_intr,
diff --git a/drivers/gpu/nvgpu/hal/mc/mc_tu104.c b/drivers/gpu/nvgpu/hal/mc/mc_tu104.c
index 646e805c9..a47ccd739 100644
--- a/drivers/gpu/nvgpu/hal/mc/mc_tu104.c
+++ b/drivers/gpu/nvgpu/hal/mc/mc_tu104.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2018-2019, NVIDIA CORPORATION.  All rights reserved.
+ * Copyright (c) 2018-2020, NVIDIA CORPORATION.  All rights reserved.
  *
  * Permission is hereby granted, free of charge, to any person obtaining a
  * copy of this software and associated documentation files (the "Software"),
@@ -28,6 +28,7 @@
 #include <nvgpu/gk20a.h>
 #include <nvgpu/engines.h>
 #include <nvgpu/gops_mc.h>
+#include <nvgpu/power_features/pg.h>
 
 #include "hal/mc/mc_gp10b.h"
 
@@ -464,3 +465,48 @@ void mc_tu104_ltc_isr(struct gk20a *g)
 		g->ops.ltc.intr.isr(g, ltc);
 	}
 }
+
+static void mc_tu104_isr_stall_primary(struct gk20a *g, u32 mc_intr_0)
+{
+	/*
+	 * In Turing, mc_intr_1 is deprecated and pbus intr is routed to
+	 * mc_intr_0. This is different than legacy chips pbus interrupt.
+	 */
+	if ((mc_intr_0 & mc_intr_pbus_pending_f()) != 0U) {
+		g->ops.bus.isr(g);
+	}
+
+	if ((mc_intr_0 & mc_intr_priv_ring_pending_f()) != 0U) {
+		g->ops.priv_ring.isr(g);
+	}
+}
+
+void mc_tu104_isr_stall(struct gk20a *g)
+{
+	u32 mc_intr_0;
+	u32 i;
+	u32 engine_id = 0U;
+	enum nvgpu_fifo_engine engine_enum;
+
+	mc_intr_0 = nvgpu_readl(g, mc_intr_r(NVGPU_MC_INTR_STALLING));
+
+	nvgpu_log(g, gpu_dbg_intr, "stall intr 0x%08x", mc_intr_0);
+
+	mc_tu104_isr_stall_primary(g, mc_intr_0);
+
+	for (i = 0U; i < g->fifo.num_engines; i++) {
+		engine_id = g->fifo.active_engines_list[i];
+
+		if ((mc_intr_0 &
+			g->fifo.engine_info[engine_id].intr_mask) == 0U) {
+			continue;
+		}
+		engine_enum = g->fifo.engine_info[engine_id].engine_enum;
+		mc_gp10b_isr_stall_engine(g, engine_enum, engine_id);
+	}
+
+	mc_gp10b_isr_stall_secondary_0(g, mc_intr_0);
+	mc_gp10b_isr_stall_secondary_1(g, mc_intr_0);
+	nvgpu_log(g, gpu_dbg_intr, "stall intr done 0x%08x", mc_intr_0);
+
+}
diff --git a/drivers/gpu/nvgpu/hal/mc/mc_tu104.h b/drivers/gpu/nvgpu/hal/mc/mc_tu104.h
index 00133b939..9e4193389 100644
--- a/drivers/gpu/nvgpu/hal/mc/mc_tu104.h
+++ b/drivers/gpu/nvgpu/hal/mc/mc_tu104.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2018-2019, NVIDIA CORPORATION.  All rights reserved.
+ * Copyright (c) 2018-2020, NVIDIA CORPORATION.  All rights reserved.
  *
  * Permission is hereby granted, free of charge, to any person obtaining a
  * copy of this software and associated documentation files (the "Software"),
@@ -63,5 +63,6 @@ bool intr_tu104_is_intr_hub_pending(struct gk20a *g, u32 mc_intr_0);
 void intr_tu104_log_pending_intrs(struct gk20a *g);
 void mc_tu104_fbpa_isr(struct gk20a *g);
 void mc_tu104_ltc_isr(struct gk20a *g);
+void mc_tu104_isr_stall(struct gk20a *g);
 
 #endif /* NVGPU_MC_TU104_H */
diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gk20a/hw_bus_gk20a.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gk20a/hw_bus_gk20a.h
index 7dee9213c..51728019f 100644
--- a/drivers/gpu/nvgpu/include/nvgpu/hw/gk20a/hw_bus_gk20a.h
+++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gk20a/hw_bus_gk20a.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2012-2019, NVIDIA CORPORATION.  All rights reserved.
+ * Copyright (c) 2012-2020, NVIDIA CORPORATION.  All rights reserved.
  *
  * Permission is hereby granted, free of charge, to any person obtaining a
  * copy of this software and associated documentation files (the "Software"),
@@ -83,8 +83,8 @@
 #define bus_intr_0_pri_squash_m()                              (U32(0x1U) << 1U)
 #define bus_intr_0_pri_fecserr_m()                             (U32(0x1U) << 2U)
 #define bus_intr_0_pri_timeout_m()                             (U32(0x1U) << 3U)
-#define bus_intr_en_0_r()                                          (0x00001140U)
-#define bus_intr_en_0_pri_squash_m()                           (U32(0x1U) << 1U)
-#define bus_intr_en_0_pri_fecserr_m()                          (U32(0x1U) << 2U)
-#define bus_intr_en_0_pri_timeout_m()                          (U32(0x1U) << 3U)
+#define bus_intr_en_1_r()                                          (0x00001144U)
+#define bus_intr_en_1_pri_squash_m()                           (U32(0x1U) << 1U)
+#define bus_intr_en_1_pri_fecserr_m()                          (U32(0x1U) << 2U)
+#define bus_intr_en_1_pri_timeout_m()                          (U32(0x1U) << 3U)
 #endif
diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gm20b/hw_bus_gm20b.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gm20b/hw_bus_gm20b.h
index dfa3a15da..3abfaa0b5 100644
--- a/drivers/gpu/nvgpu/include/nvgpu/hw/gm20b/hw_bus_gm20b.h
+++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gm20b/hw_bus_gm20b.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2014-2019, NVIDIA CORPORATION.  All rights reserved.
+ * Copyright (c) 2014-2020, NVIDIA CORPORATION.  All rights reserved.
  *
  * Permission is hereby granted, free of charge, to any person obtaining a
  * copy of this software and associated documentation files (the "Software"),
@@ -100,8 +100,8 @@
 #define bus_intr_0_pri_squash_m()                              (U32(0x1U) << 1U)
 #define bus_intr_0_pri_fecserr_m()                             (U32(0x1U) << 2U)
 #define bus_intr_0_pri_timeout_m()                             (U32(0x1U) << 3U)
-#define bus_intr_en_0_r()                                          (0x00001140U)
-#define bus_intr_en_0_pri_squash_m()                           (U32(0x1U) << 1U)
-#define bus_intr_en_0_pri_fecserr_m()                          (U32(0x1U) << 2U)
-#define bus_intr_en_0_pri_timeout_m()                          (U32(0x1U) << 3U)
+#define bus_intr_en_1_r()                                          (0x00001144U)
+#define bus_intr_en_1_pri_squash_m()                           (U32(0x1U) << 1U)
+#define bus_intr_en_1_pri_fecserr_m()                          (U32(0x1U) << 2U)
+#define bus_intr_en_1_pri_timeout_m()                          (U32(0x1U) << 3U)
 #endif
diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gp10b/hw_bus_gp10b.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gp10b/hw_bus_gp10b.h
index 92feef152..e59251536 100644
--- a/drivers/gpu/nvgpu/include/nvgpu/hw/gp10b/hw_bus_gp10b.h
+++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gp10b/hw_bus_gp10b.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2014-2019, NVIDIA CORPORATION.  All rights reserved.
+ * Copyright (c) 2014-2020, NVIDIA CORPORATION.  All rights reserved.
  *
  * Permission is hereby granted, free of charge, to any person obtaining a
  * copy of this software and associated documentation files (the "Software"),
@@ -100,8 +100,8 @@
 #define bus_intr_0_pri_squash_m()                              (U32(0x1U) << 1U)
 #define bus_intr_0_pri_fecserr_m()                             (U32(0x1U) << 2U)
 #define bus_intr_0_pri_timeout_m()                             (U32(0x1U) << 3U)
-#define bus_intr_en_0_r()                                          (0x00001140U)
-#define bus_intr_en_0_pri_squash_m()                           (U32(0x1U) << 1U)
-#define bus_intr_en_0_pri_fecserr_m()                          (U32(0x1U) << 2U)
-#define bus_intr_en_0_pri_timeout_m()                          (U32(0x1U) << 3U)
+#define bus_intr_en_1_r()                                          (0x00001144U)
+#define bus_intr_en_1_pri_squash_m()                           (U32(0x1U) << 1U)
+#define bus_intr_en_1_pri_fecserr_m()                          (U32(0x1U) << 2U)
+#define bus_intr_en_1_pri_timeout_m()                          (U32(0x1U) << 3U)
 #endif
diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_bus_gv11b.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_bus_gv11b.h
index d73e60f92..182705a4f 100644
--- a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_bus_gv11b.h
+++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_bus_gv11b.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2016-2019, NVIDIA CORPORATION.  All rights reserved.
+ * Copyright (c) 2016-2020, NVIDIA CORPORATION.  All rights reserved.
  *
  * Permission is hereby granted, free of charge, to any person obtaining a
  * copy of this software and associated documentation files (the "Software"),
@@ -100,10 +100,10 @@
 #define bus_intr_0_pri_squash_m()                              (U32(0x1U) << 1U)
 #define bus_intr_0_pri_fecserr_m()                             (U32(0x1U) << 2U)
 #define bus_intr_0_pri_timeout_m()                             (U32(0x1U) << 3U)
-#define bus_intr_en_0_r()                                          (0x00001140U)
-#define bus_intr_en_0_pri_squash_m()                           (U32(0x1U) << 1U)
-#define bus_intr_en_0_pri_fecserr_m()                          (U32(0x1U) << 2U)
-#define bus_intr_en_0_pri_timeout_m()                          (U32(0x1U) << 3U)
+#define bus_intr_en_1_r()                                          (0x00001144U)
+#define bus_intr_en_1_pri_squash_m()                           (U32(0x1U) << 1U)
+#define bus_intr_en_1_pri_fecserr_m()                          (U32(0x1U) << 2U)
+#define bus_intr_en_1_pri_timeout_m()                          (U32(0x1U) << 3U)
 #define bus_debug_sel_0_r()                                        (0x000010a0U)
 #define bus_debug_sel_1_r()                                        (0x000010a4U)
 #define bus_debug_sel_2_r()                                        (0x000010a8U)
diff --git a/userspace/units/bus/nvgpu-bus.c b/userspace/units/bus/nvgpu-bus.c
index 68b776879..60c146c61 100644
--- a/userspace/units/bus/nvgpu-bus.c
+++ b/userspace/units/bus/nvgpu-bus.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2019, NVIDIA CORPORATION.  All rights reserved.
+ * Copyright (c) 2019-2020, NVIDIA CORPORATION.  All rights reserved.
  *
  * Permission is hereby granted, free of charge, to any person obtaining a
  * copy of this software and associated documentation files (the "Software"),
@@ -125,8 +125,8 @@ int test_bus_setup(struct unit_module *m, struct gk20a *g, void *args)
 	g->ops.bus.bar1_bind = gm20b_bus_bar1_bind;
 	g->ops.bus.bar2_bind = gp10b_bus_bar2_bind;
 	g->ops.bus.configure_debug_bus = gv11b_bus_configure_debug_bus;
-	g->ops.mc.intr_stall_unit_config =
-					mc_gp10b_intr_stall_unit_config;
+	g->ops.mc.intr_nonstall_unit_config =
+					mc_gp10b_intr_nonstall_unit_config;
 	g->ops.ptimer.isr = gk20a_ptimer_isr;
 
 	/* Map register space NV_PRIV_MASTER */
@@ -181,7 +181,7 @@ int test_init_hw(struct unit_module *m, struct gk20a *g, void *args)
 	p->is_silicon = false;
 	g->ops.bus.configure_debug_bus = NULL;
 	ret = g->ops.bus.init_hw(g);
-	assert(nvgpu_readl(g, bus_intr_en_0_r()) == 0U);
+	assert(nvgpu_readl(g, bus_intr_en_1_r()) == 0U);
 	assert(nvgpu_readl(g, bus_debug_sel_0_r()) == 0xFU);
 	assert(nvgpu_readl(g, bus_debug_sel_1_r()) == 0xFU);
 	assert(nvgpu_readl(g, bus_debug_sel_2_r()) == 0xFU);
@@ -190,7 +190,7 @@ int test_init_hw(struct unit_module *m, struct gk20a *g, void *args)
 	p->is_silicon = true;
 	g->ops.bus.configure_debug_bus = gv11b_bus_configure_debug_bus;
 	ret = g->ops.bus.init_hw(g);
-	assert(nvgpu_readl(g, bus_intr_en_0_r()) == 0xEU);
+	assert(nvgpu_readl(g, bus_intr_en_1_r()) == 0xEU);
 	assert(nvgpu_readl(g, bus_debug_sel_0_r()) == 0x0U);
 	assert(nvgpu_readl(g, bus_debug_sel_1_r()) == 0x0U);
 	assert(nvgpu_readl(g, bus_debug_sel_2_r()) == 0x0U);
@@ -199,7 +199,7 @@ int test_init_hw(struct unit_module *m, struct gk20a *g, void *args)
 	p->is_fpga = true;
 	p->is_silicon = false;
 	ret = g->ops.bus.init_hw(g);
-	assert(nvgpu_readl(g, bus_intr_en_0_r()) == 0xEU);
+	assert(nvgpu_readl(g, bus_intr_en_1_r()) == 0xEU);
 	ret = UNIT_SUCCESS;
 done:
 	return ret;
diff --git a/userspace/units/mc/nvgpu-mc.c b/userspace/units/mc/nvgpu-mc.c
index 4297089a6..5a30a9168 100644
--- a/userspace/units/mc/nvgpu-mc.c
+++ b/userspace/units/mc/nvgpu-mc.c
@@ -492,7 +492,10 @@ int test_isr_stall(struct unit_module *m, struct gk20a *g, void *args)
 	nvgpu_posix_io_writel_reg_space(g, mc_intr_ltc_r(), 1U);
 	reset_ctx();
 	g->ops.mc.isr_stall(g);
-	if (!u.bus_isr || !u.ce_isr || !u.fb_isr || !u.fifo_isr || !u.gr_isr ||
+	if (u.bus_isr) {
+		unit_return_fail(m, "BUS ISR called from Stall\n");
+	}
+	if (!u.ce_isr || !u.fb_isr || !u.fifo_isr || !u.gr_isr ||
 	    !u.pmu_isr || !u.priv_ring_isr) {
 		unit_return_fail(m, "not all ISRs called\n");
 	}
@@ -599,7 +602,7 @@ int test_isr_nonstall(struct unit_module *m, struct gk20a *g, void *args)
 	u.fifo_isr_return = 0x2;
 	u.gr_isr_return = 0x4;
 	val = g->ops.mc.isr_nonstall(g);
-	if (!u.ce_isr || !u.fifo_isr || !u.gr_isr) {
+	if (!u.bus_isr || !u.ce_isr || !u.fifo_isr || !u.gr_isr) {
 		unit_return_fail(m, "not all ISRs called\n");
 	}
 	if (val != 0x7) {